{"id":13427781,"url":"https://github.com/chipsalliance/riscv-dv","last_synced_at":"2025-05-14T13:07:51.055Z","repository":{"id":38190476,"uuid":"167140400","full_name":"chipsalliance/riscv-dv","owner":"chipsalliance","description":"Random instruction generator for RISC-V processor verification","archived":false,"fork":false,"pushed_at":"2025-02-07T09:50:06.000Z","size":10738,"stargazers_count":1090,"open_issues_count":136,"forks_count":337,"subscribers_count":82,"default_branch":"master","last_synced_at":"2025-04-15T03:37:36.299Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-01-23T07:47:20.000Z","updated_at":"2025-04-11T16:39:44.000Z","dependencies_parsed_at":"2023-09-26T16:42:53.296Z","dependency_job_id":"e3f41b26-d21a-4489-b0de-9a45c0e57ce0","html_url":"https://github.com/chipsalliance/riscv-dv","commit_stats":null,"previous_names":["google/riscv-dv"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Friscv-dv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Friscv-dv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Friscv-dv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Friscv-dv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/riscv-dv/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254149959,"owners_count":22022851,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-07-31T01:00:40.331Z","updated_at":"2025-05-14T13:07:46.045Z","avatar_url":"https://github.com/chipsalliance.png","language":"Python","funding_links":[],"categories":["Python","Verification Frameworks","Verification","Hardware Verification"],"sub_categories":["Tools"],"readme":"## Overview\n\nRISCV-DV is a SV/UVM based open-source instruction generator for RISC-V\nprocessor verification. It currently supports the following features:\n\n- Supported instruction set: RV32IMAFDC, RV64IMAFDC\n- Supported privileged mode: machine mode, supervisor mode, user mode\n- Page table randomization and exception\n- Privileged CSR setup randomization\n- Privileged CSR test suite\n- Trap/interrupt handling\n- Test suite to stress test MMU\n- Sub-program generation and random program calls\n- Illegal instruction and HINT instruction generation\n- Random forward/backward branch instructions\n- Supports mixing directed instructions with random instruction stream\n- Debug mode support, with fully randomized debug ROM\n- Instruction generation coverage model\n- Handshake communication with testbench\n- Support handcoded assembly test\n- Co-simulation with multiple ISS : spike, riscv-ovpsim, whisper, sail-riscv\n\n## Getting Started\n\n### Prerequisites\n\nTo be able to run the instruction generator, you need to have an RTL simulator\nwhich supports SystemVerilog and UVM 1.2. This generator has been verified with\nSynopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.\nPlease make sure the EDA tool environment is properly setup before running the generator.\n\n### Install RISCV-DV\n\nGetting the source\n```bash\ngit clone https://github.com/google/riscv-dv.git\n```\n\nThere are two ways that you can run scripts from riscv-dv.\n\nFor developers which may work on multiple clones in parallel, using directly run\nby `python3` script is highly recommended. Example:\n\n```bash\npip3 install -r requirements.txt    # install dependencies (only once)\npython3 run.py --help\n```\nFor normal users, using the python package is recommended. First, cd to the directory\nwhere riscv-dv is cloned and run:\n\n```bash\nexport PATH=$HOME/.local/bin/:$PATH  # add ~/.local/bin to the $PATH (only once)\npip3 install --user -e .\n```\n\nThis installs riscv-dv in a mode where any changes within the repo are immediately\navailable simply by running `run`/`cov`. There is no need to repeatedly run `pip install .`\nafter each change. Example for running:\n\n```bash\nrun --help\ncov --help\n```\n\nUse below command to install Verible, which is the tool to check Verilog style\n```bash\nverilog_style/build-verible.sh\n```\n\nThis is the command to run Verilog style check. It's recommended to run and clean up\nall the style violations before submit a PR\n```bash\nverilog_style/run.sh\n```\n\n## Document\n\nTo understand how to setup and customize the generator, please check the full\ndocument under docs directory. You can use the makefile to generate the\ndocument. [HTML\npreview](https://htmlpreview.github.io/?https://github.com/google/riscv-dv/blob/master/docs/build/singlehtml/index.html#document-index).\nYou can find the prebuilt document under docs/build/singlehtml/index.html\n\n## External contributions and collaborations\n\nRISC-V DV is now contributed to CHIPS Alliance. We have regular meetings to\ndiscuss the issues, feature priorities, development progress etc. Please join\nthe [mail group](https://lists.chipsalliance.org/g/riscv-dv-wg) for latest\nstatus.\n\nPlease refer to CONTRIBUTING.md for license related questions.\n\n## Supporting model\n\nPlease file an issue under this repository for any bug report / integration\nissue / feature request. We are looking forward to knowing your experience of\nusing this flow and how we can make it better together.\n\n## Disclaimer\n\nThis is not an officially supported Google product.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Friscv-dv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Friscv-dv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Friscv-dv/lists"}