{"id":13427682,"url":"https://github.com/chipsalliance/rocket-chip","last_synced_at":"2025-12-17T20:05:35.338Z","repository":{"id":20667807,"uuid":"23950406","full_name":"chipsalliance/rocket-chip","owner":"chipsalliance","description":"Rocket Chip Generator","archived":false,"fork":false,"pushed_at":"2025-04-17T18:56:05.000Z","size":21752,"stargazers_count":3417,"open_issues_count":305,"forks_count":1160,"subscribers_count":196,"default_branch":"master","last_synced_at":"2025-04-24T06:58:35.042Z","etag":null,"topics":["chip-generator","chisel","riscv","rocket-chip","rtl","scala"],"latest_commit_sha":null,"homepage":null,"language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE.Berkeley","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2014-09-12T07:04:30.000Z","updated_at":"2025-04-24T04:58:21.000Z","dependencies_parsed_at":"2024-05-21T02:47:25.082Z","dependency_job_id":"09d80875-0b85-4973-bcff-4a43f8c1d037","html_url":"https://github.com/chipsalliance/rocket-chip","commit_stats":{"total_commits":7508,"total_committers":201,"mean_commits":"37.353233830845774","dds":0.8229888119339371,"last_synced_commit":"e3773366a5c473b6b45107f037e3130f4d667238"},"previous_names":["freechipsproject/rocket-chip"],"tags_count":22,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Frocket-chip","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Frocket-chip/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Frocket-chip/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Frocket-chip/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/rocket-chip/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250832551,"owners_count":21494612,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chip-generator","chisel","riscv","rocket-chip","rtl","scala"],"created_at":"2024-07-31T01:00:37.735Z","updated_at":"2025-12-17T20:05:35.215Z","avatar_url":"https://github.com/chipsalliance.png","language":"Scala","funding_links":[],"categories":["CPU cores","Scala","CPUs","Open Source Implementations","CPU RISC-V","Open Source implementations","Applications","Open Source Core Implementations"],"sub_categories":["Cores","网络服务_其他"],"readme":"Rocket Chip Generator :rocket: ![Build Status](https://github.com/chipsalliance/rocket-chip/workflows/Continuous%20Integration/badge.svg?branch=master)\n=====================\n\nThis repository contains the Rocket chip generator necessary to instantiate\nthe RISC-V Rocket Core. For more information on Rocket Chip, please consult our [technical report](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html).\n\n## RocketChip Dev Meeting\n\nRocketChip development meetings happen every 2 weeks on Wednesday 17:00 – 18:00am CST (Pacific Time - Los Angeles) with meeting notes [here](https://docs.google.com/document/d/1NjDnf-i10QE0y-qI94A67uCspDRdCIS_IRTm4jc0Ycc):\n- Click [here](https://calendar.google.com/calendar/ical/c_699527d804418f900468a49b413d1f9c08e13c0f3f872ce551fc0470d4cdf983%40group.calendar.google.com/public/basic.ics) to subscribe Meeting Schedule(iCal format)\n- Click [here](https://calendar.google.com/calendar/embed?src=c_699527d804418f900468a49b413d1f9c08e13c0f3f872ce551fc0470d4cdf983%40group.calendar.google.com) to view Meeting Schedule via Google Calendar\n- Click [here](https://sifive.zoom.us/j/93899365000?pwd=UG1HSFJ4ODFzR2dhMHU2bUNqbXc3Zz09) to join Zoom meeting (ID: 93899365000, passcode: 754340)\n\nFor possible time adjustments, they will be negotiated in Slack and published in the calendar.\n\n## Table of Contents\n\n+ [Quick instructions](#quick) for those who want to dive directly into the details without knowing exactly what's in the repository.\n+ [What's in the Rocket chip generator repository?](#what)\n+ [How should I use the Rocket chip generator?](#how)\n    + [Using the cycle-accurate Verilator simulation](#emulator)\n    + [Mapping a Rocket core down to an FPGA](#fpga)\n    + [Pushing a Rocket core through the VLSI tools](#vlsi)\n+ [How can I parameterize my Rocket chip?](#param)\n+ [Debugging with GDB](#debug)\n+ [Building Rocket Chip with an IDE](#ide)\n+ [Contributors](#contributors)\n\n## \u003ca name=\"quick\"\u003e\u003c/a\u003e Quick Instructions\n\n### Checkout The Code\n\n    $ git clone https://github.com/ucb-bar/rocket-chip.git\n    $ cd rocket-chip\n    $ git submodule update --init\n\n### Install Necessary Dependencies\n\nYou may need to install some additional packages to use this repository.\nRather than list all dependencies here, please see the appropriate section of the READMEs for each of the subprojects:\n\n* [rocket-tools \"Ubuntu Packages Needed\"](https://github.com/freechipsproject/rocket-tools/blob/master/README.md)\n* [chisel3 \"Installation\"](https://github.com/ucb-bar/chisel3#installation)\n\n### Building The Project\n\nGenerating verilog\n\n    $ make verilog\n\nGenerating verilog for a specific Config\n\n    $ make verilog CONFIG=DefaultSmallConfig\n\n### Keeping Your Repo Up-to-Date\n\nIf you are trying to keep your repo up to date with this GitHub repo,\nyou also need to keep the submodules and tools up to date.\n\n    $ # Get the newest versions of the files in this repo\n    $ git pull origin master\n    $ # Make sure the submodules have the correct versions\n    $ git submodule update --init --recursive\n\nIf rocket-tools version changes, you should recompile and install rocket-tools according to the directions in the [rocket-tools/README](https://github.com/freechipsproject/rocket-tools/blob/master/README.md).\n\n    $ cd rocket-tools\n    $ ./build.sh\n    $ ./build-rv32ima.sh (if you are using RV32)\n\n## \u003ca name=\"what\"\u003e\u003c/a\u003e What's in the Rocket chip generator repository?\n\nThe rocket-chip repository is a meta-repository that points to several\nsub-repositories using [Git submodules](http://git-scm.com/book/en/Git-Tools-Submodules).\nThose repositories contain tools needed to generate and test SoC designs.\nThis respository also contains code that is used to generate RTL.\nHardware generation is done using [Chisel](http://chisel.eecs.berkeley.edu),\na hardware construction language embedded in Scala.\nThe rocket-chip generator is a Scala program that invokes the Chisel compiler\nin order to emit RTL describing a complete SoC.\nThe following sections describe the components of this repository.\n\n### \u003ca name=\"what_submodules\"\u003e\u003c/a\u003eGit Submodules\n\n[Git submodules](https://git-scm.com/book/en/v2/Git-Tools-Submodules) allow you to keep a Git repository as a subdirectory of another Git repository.\nFor projects being co-developed with the Rocket Chip Generator, we have often found it expedient to track them as submodules,\nallowing for rapid exploitation of new features while keeping commit histories separate.\nAs submoduled projects adopt stable public APIs, we transition them to external dependencies.\nHere are the submodules that are currently being tracked in the rocket-chip repository:\n\n* **chisel3**\n([https://github.com/ucb-bar/chisel3](https://github.com/ucb-bar/chisel3)):\nThe Rocket Chip Generator uses [Chisel](http://chisel.eecs.berkeley.edu) to generate RTL.\n* **firrtl**\n([https://github.com/ucb-bar/firrtl](https://github.com/ucb-bar/firrtl)):\n[Firrtl (Flexible Internal Representation for RTL)](http://bar.eecs.berkeley.edu/projects/2015-firrtl.html)\nis the intermediate representation of RTL constructions used by Chisel3.\nThe Chisel3 compiler generates a Firrtl representation,\nfrom which the final product (Verilog code, C code, etc) is generated.\n* **hardfloat**\n([https://github.com/ucb-bar/berkeley-hardfloat](https://github.com/ucb-bar/berkeley-hardfloat)):\nHardfloat holds Chisel code that generates parameterized IEEE 754-2008 compliant\nfloating-point units used for fused multiply-add operations, conversions\nbetween integer and floating-point numbers, and conversions between\nfloating-point conversions with different precision.\n* **rocket-tools**\n([https://github.com/freechipsproject/rocket-tools](https://github.com/freechipsproject/rocket-tools)):\nWe tag a version of RISC-V software tools that work with the RTL committed in this repository.\n* **torture**\n([https://github.com/ucb-bar/riscv-torture](https://github.com/ucb-bar/riscv-torture)):\nThis module is used to generate and execute constrained random instruction streams that can\nbe used to stress-test both the core and uncore portions of the design.\n\n### \u003ca name=\"what_packages\"\u003e\u003c/a\u003eScala Packages\n\nIn addition to submodules that track independent Git repositories,\nthe rocket-chip code base is itself factored into a number of Scala packages.\nThese packages are all found within the src/main/scala directory.\nSome of these packages provide Scala utilities for generator configuration,\nwhile other contain the actual Chisel RTL generators themselves.\nHere is a brief description of what can be found in each package:\n\n* **amba**\nThis RTL package uses diplomacy to generate bus implementations of AMBA protocols, including AXI4, AHB-lite, and APB.\n* **config**\nThis utility package provides Scala interfaces for configuring a generator via a dynamically-scoped\nparameterization library.\n* **coreplex**\nThis RTL package generates a complete coreplex by gluing together a variety of components from other packages,\nincluding: tiled Rocket cores, a system bus network, coherence agents, debug devices, interrupt handlers, externally-facing peripherals,\nclock-crossers and converters from TileLink to external bus protocols (e.g. AXI or AHB).\n* **devices**\nThis RTL package contains implementations for peripheral devices, including the Debug module and various TL slaves.\n* **diplomacy**\nThis utility package extends Chisel by allowing for two-phase hardware elaboration, in which certain parameters\nare dynamically negotiated between modules. For more information about diplomacy, see [this paper](https://carrv.github.io/2017/papers/cook-diplomacy-carrv2017.pdf).\n* **groundtest**\nThis RTL package generates synthesizable hardware testers that emit randomized\nmemory access streams in order to stress-tests the uncore memory hierarchy.\n* **jtag**\nThis RTL package provides definitions for generating JTAG bus interfaces.\n* **regmapper**\nThis utility package generates slave devices with a standardized interface for accessing their memory-mapped registers.\n* **rocket**\nThis RTL package generates the Rocket in-order pipelined core,\nas well as the L1 instruction and data caches.\nThis library is intended to be used by a chip generator that instantiates the\ncore within a memory system and connects it to the outside world.\n* **tile**\nThis RTL package contains components that can be combined with cores to construct tiles, such as FPUs and accelerators.\n* **tilelink**\nThis RTL package uses diplomacy to generate bus implementations of the TileLink protocol. It also contains a variety\nof adapters and protocol converters.\n* **system**\nThis top-level utility package invokes Chisel to elaborate a particular configuration of a coreplex,\nalong with the appropriate testing collateral.\n* **unittest**\nThis utility package contains a framework for generateing synthesizable hardware testers of individual modules.\n* **util**\nThis utility package provides a variety of common Scala and Chisel constructs that are re-used across\nmultiple other packages,\n\n### \u003ca name=\"what_else\"\u003e\u003c/a\u003eOther Resources\n\nOutside of Scala, we also provide a variety of resources to create a complete SoC implementation and\ntest the generated designs.\n\n* **bootrom**\nSources for the first-stage bootloader included in the BootROM.\n* **csrc**\nC sources for use with Verilator simulation.\n* **docs**\nDocumentation, tutorials, etc for specific parts of the codebase.\n* **emulator**\nDirectory in which Verilator simulations are compiled and run.\n* **regression**\nDefines continuous integration and nightly regression suites.\n* **scripts**\nUtilities for parsing the output of simulations or manipulating the contents of source files.\n* **vsim**\nDirectory in which Synopsys VCS simulations are compiled and run.\n* **vsrc**\nVerilog sources containing interfaces, harnesses and VPI.\n\n## \u003ca name=\"ide\"\u003e\u003c/a\u003e IDEs Support\n\nThe Rocket Chip Scala build uses [mill](https://github.com/com-lihaoyi/mill) as build tool.\n\nIDEs like [IntelliJ](https://www.jetbrains.com/idea/) and [VSCode](https://code.visualstudio.com/) are popular in the Scala community and work with Rocket Chip.\n\nThe Rocket Chip currently uses `nix` to configure the build and/or development environment, you need to install it first depending on your OS distro.\n\nThen follow the steps:\n\n1. Generate BSP config by running:\n\n   ```\n   mill mill.bsp.BSP/install\n   ```\n\n2. Patch the `argv` in `.bsp/mill-bsp.json`, from\n\n   ```json\n   {\"name\":\"mill-bsp\",\"argv\":[\"/usr/bin/mill\",\"--bsp\",\"--disable-ticker\",\"--color\",\"false\",\"--jobs\",\"1\"],\"millVersion\":\"0.10.9\",\"bspVersion\":\"2.0.0\",\"languages\":[\"scala\",\"java\"]}\n   ```\n\n   to\n\n   ```json\n   {\"name\":\"mill-bsp\",\"argv\":[\"/usr/bin/nix\",\"develop\",\"-c\",\"mill\",\"--bsp\",\"--disable-ticker\",\"--color\",\"false\",\"--jobs\",\"1\"],\"millVersion\":\"0.10.9\",\"bspVersion\":\"2.0.0\",\"languages\":[\"scala\",\"java\"]}\n   ```\n   \n### For IntelliJ users\n\n3. Install and configure [Scala](https://plugins.jetbrains.com/plugin/1347-scala) plugin.\n\n4. BSP should be automatically run.\n   If it doesn't, click `bsp` on the right bar, then right-click on your project to reload.\n\n### For VSCode users\n\n3. Install and configure [Metals](https://marketplace.visualstudio.com/items?itemName=scalameta.metals) extension.\n\n4. Execute VSCode command `Metals: Import build`.\n\n## \u003ca name=\"contributors\"\u003e\u003c/a\u003e Contributors\n\nContributing guidelines can be found in [CONTRIBUTING.md](CONTRIBUTING.md).\n\nA list of contributors can be found [here](https://github.com/chipsalliance/rocket-chip/graphs/contributors).\n\n## \u003ca name=\"attribution\"\u003e\u003c/a\u003e Attribution\n\nIf used for research, please cite Rocket Chip by the technical report:\n\nKrste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, _[The Rocket Chip Generator](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html)_, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Frocket-chip","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Frocket-chip","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Frocket-chip/lists"}