{"id":13649142,"url":"https://github.com/chipsalliance/sv-tests","last_synced_at":"2026-01-28T10:32:02.689Z","repository":{"id":37053529,"uuid":"201299456","full_name":"chipsalliance/sv-tests","owner":"chipsalliance","description":"Test suite designed to check compliance with the SystemVerilog standard.","archived":false,"fork":false,"pushed_at":"2025-04-09T22:40:56.000Z","size":12773,"stargazers_count":312,"open_issues_count":69,"forks_count":78,"subscribers_count":18,"default_branch":"master","last_synced_at":"2025-04-10T00:38:52.953Z","etag":null,"topics":["compliance-testing","hdl","rtl","symbiflow","systemverilog","verilog"],"latest_commit_sha":null,"homepage":"https://chipsalliance.github.io/sv-tests-results/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"isc","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":"AUTHORS","dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-08-08T16:45:56.000Z","updated_at":"2025-04-09T22:13:14.000Z","dependencies_parsed_at":"2023-10-03T05:38:38.519Z","dependency_job_id":"9a556122-e578-46b9-b1cf-f9b389bfb8b4","html_url":"https://github.com/chipsalliance/sv-tests","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Fsv-tests","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Fsv-tests/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Fsv-tests/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Fsv-tests/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/sv-tests/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248138003,"owners_count":21053775,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["compliance-testing","hdl","rtl","symbiflow","systemverilog","verilog"],"created_at":"2024-08-02T01:04:48.197Z","updated_at":"2026-01-28T10:32:02.659Z","avatar_url":"https://github.com/chipsalliance.png","language":"SystemVerilog","funding_links":[],"categories":["SystemVerilog","Benchmarks"],"sub_categories":[],"readme":"# SystemVerilog Tester\n\n[![License](https://img.shields.io/github/license/chipsalliance/sv-tests.svg)](https://github.com/chipsalliance/sv-tests/blob/master/LICENSE)\n[![Build Status](https://github.com/chipsalliance/sv-tests/workflows/sv-tests-ci/badge.svg?branch=master)](https://github.com/chipsalliance/sv-tests/actions)\n\nThe purpose of this project is to find all the supported and missing SystemVerilog features in various Verilog tools.\n\nThe report generated from the last passing master build can be viewed [on a dedicated dashboard:](https://chipsalliance.github.io/sv-tests-results/)\n[![Grid](./img/sv-test-grid.png)](https://chipsalliance.github.io/sv-tests-results/)\n\nHistory of the builds is also tracked and can be seen [on a separate page:](https://chipsalliance.github.io/sv-tests-results/history)\n[![History](./img/sv-test-history.png)](https://chipsalliance.github.io/sv-tests-results/history)\n\n# Running\n\nInitialize the submodules:\n\n```bash\ngit submodule update --init --recursive\n```\n\nInstall all the python dependencies and make sure the installed binaries can be called.\n\n```bash\npip3 install --user -r conf/requirements.txt\nexport PATH=~/.local/bin:$PATH\n```\n\nBuild tools (optional, tools from `PATH` can be used):\n\n```bash\nmake -k runners\n```\n\nAnd then just run:\n\n```bash\nmake generate-tests -j$(nproc)\nmake -j$(nproc)\n```\n\nThis should generate many log files for all the tools/tests combinations and an `out/report.html` file with a summary of the tested features and tools.\n\nIf you don't want to generate the report file, but are interested in just running all the tests, you can run:\n\n```bash\nmake tests\n```\n\n## Adding new test cases\n\nAdding a new test case is a two step process.\nFirst you create the test case itself which should use only a minimal required subset of SystemVerilog to test a particular feature.\nAdditionally each test should cover only a single feature.\nIf the test must use several features, each of those must be also covered in separate test cases.\n\nAfter creating a new test case it must be correctly tagged:\n\n* `name` - must be unique and should be directly related to what the test case covers.\n* `description` - should provide a short description that will be visible in the report page.\n* `should_fail_because` - must be used if the test is expected to fail and should contain the reason of failure.\n* `files` - is a list of files used by this test case, can be omitted to use only the main file with metadata.\n* `incdirs` - can be used to provide a list of include directories, can be omitted to use only the default ones.\n* `top_module` - optional, allows to specify which module is the top one.\n* `tags` - tag must be used to specify which part of SystemVerilog specification this test case covers.\n* `defines` - provides a list of macros for preprocessor.\n  If the test case uses several SystemVerilog features, only the feature directly tested should be included in tags.\n  List of existing tags is located in `conf/lrm.conf`.\n\nFinally the file containing the test case and metadata should be placed in `tests/chapter-([0-9]+)/` subdirectory based on the `tags` fields specified earlier.\n\n## Importing existing tests from a test suite/core/tool\n\n1. Add the tests as a submodule to this repository via `git submodule add \u003cgit_url\u003e third_party/\u003ccategory\u003e/\u003cname\u003e`.\n   If you want to add tests from a tool that is already in `third_party/tools` you can skip this step.\n2. Add a new tag named `\u003cname\u003e` to `conf/lrm.conf` together with a short description.\n3. Generate wrapper `.sv` files by either:\n   * Adding a new config to `conf/generators/meta-path/` that will be used by `generators/path_generator`.\n   * Adding a new generator script to `generators/` that will create required wrappers.\n\n   First method works well with test suites in which each test case is contained in a separate Verilog file.\n   If the test suite provides metadata that must be processed or you are importing an IP core then you should create custom generator script.\n\n   Use tag that you added in the previous step.\n\n## Adding a new tool\n\n1. Add the tool as a submodule to this repository via `git submodule add \u003cgit_url\u003e third_party/tools/\u003cname\u003e`.\n2. Add a target for building and installing the tool manually in `tools/runners.mk`\n3. Create a new runner script in `tools/runners/\u003cname\u003e.py` that will contain a subclass of `BaseRunner` named `\u003cname\u003e`.\n   This subclass will need to at least implement the following methods:\n   * `__init__` to provide general information about the tool.\n   * `prepare_run_cb` to prepare correct tool invocation that will be used during tests.\n\n   If the new tool is a Python library, reimplement `run` and other supporting methods instead of implementing `prepare_run_cb`.\n\n## Supported tools\n\n* [Yosys](https://github.com/yosysHQ/yosys)\n* [Odin II](https://verilogtorouting.org)\n* [Verilator](https://verilator.org)\n* [Icarus](http://iverilog.icarus.com)\n* [slang](https://github.com/MikePopoloski/slang)\n* [sv2v(zachjs)](https://github.com/zachjs/sv2v)\n* [tree-sitter-systemverilog](https://github.com/gmlarumbe/tree-sitter-systemverilog)\n* [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog)\n* [sv-parser](https://github.com/dalance/sv-parser)\n* [moore](http://llhd.io)\n* [verible](https://github.com/google/verible)\n* [circt-verilog](https://github.com/llvm/circt)\n* [yosys-slang](https://github.com/povik/yosys-slang)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Fsv-tests","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Fsv-tests","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Fsv-tests/lists"}