{"id":13408080,"url":"https://github.com/clin99/awesome-eda","last_synced_at":"2026-01-04T14:04:53.230Z","repository":{"id":80934749,"uuid":"193008083","full_name":"clin99/awesome-eda","owner":"clin99","description":null,"archived":false,"fork":false,"pushed_at":"2019-06-26T20:20:17.000Z","size":53,"stargazers_count":90,"open_issues_count":0,"forks_count":16,"subscribers_count":16,"default_branch":"master","last_synced_at":"2024-10-30T08:16:49.051Z","etag":null,"topics":["circuit","eda","fpga","gds","lithography","logic-synthesis","open-source","parser","placement","routing","simulation","static-timing-analysis","systemverilog","timer","verification","verilog"],"latest_commit_sha":null,"homepage":null,"language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/clin99.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2019-06-21T01:15:18.000Z","updated_at":"2024-10-03T15:31:24.000Z","dependencies_parsed_at":"2023-03-23T02:30:57.667Z","dependency_job_id":null,"html_url":"https://github.com/clin99/awesome-eda","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/clin99%2Fawesome-eda","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/clin99%2Fawesome-eda/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/clin99%2Fawesome-eda/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/clin99%2Fawesome-eda/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/clin99","download_url":"https://codeload.github.com/clin99/awesome-eda/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244312968,"owners_count":20433002,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["circuit","eda","fpga","gds","lithography","logic-synthesis","open-source","parser","placement","routing","simulation","static-timing-analysis","systemverilog","timer","verification","verilog"],"created_at":"2024-07-30T20:00:50.620Z","updated_at":"2026-01-04T14:04:53.166Z","avatar_url":"https://github.com/clin99.png","language":null,"funding_links":[],"categories":["🌍 Awesome Digital IC Resources","Others","Awesome List","Awesome Awesome ⭐"],"sub_categories":["Physical Design"],"readme":"# Awesome Open Source EDA Projects\n\u003e A curated list of EDA open source projects. \nPlease feel free to update this page through [submitting pull requests][GitHub pull requests] or [emailing me][email me].\n\n## Table of Contents\n* [1999](#1999) \n* [2002](#2002) \n* [2004](#2004) \n* [2005](#2005) \n* [2009](#2009) \n* [2010](#2010) \n* [2011](#2011) \n* [2012](#2012) \n* [2013](#2013) \n* [2014](#2014) \n* [2015](#2015) \n* [2016](#2016) \n* [2017](#2017) \n* [2018](#2018) \n* [2019](#2019) \n* [Summary](#summary) \n* [Reference](#reference)\n\n\n## Projects (sorted by year)\n\n### 1999\n* [ngspice](https://github.com/imr/ngspice)\n\n### 2002\n* [xyce](https://xyce.sandia.gov/)\n\n### 2004\n* [Hierarchical Asynchronous Circuit Kompiler Toolkit](https://github.com/fangism/hackt)\n\n### 2005\n* [Berkeley-abc](https://github.com/berkeley-abc/abc)\n\n### 2009\n* [CVC4](https://github.com/CVC4/CVC4)\n\n### 2010\n* [Galois Parallel Framework](https://github.com/IntelligentSoftwareSystems/Galois)\n\n### 2011\n* [Asynchronous Circuit Compiler](https://github.com/asyncvlsi/act)\n\n### 2012\n* [PyMTL: Python-based hardware modeling framework](https://github.com/cornell-brg/pymtl)\n* [Yosys Open SYnthesis Suite](https://github.com/YosysHQ/yosys)\n* [Verilog to Routing -- Open Source CAD Flow for FPGA Research](https://github.com/verilog-to-routing/vtr-verilog-to-routing)\n\n### 2013\n* [Qrouter](http://opencircuitdesign.com/qrouter/2013)\n\n### 2014\n* [Graywolf](https://github.com/rubund/graywolf2014)\n* [Limbo](https://github.com/limbo018/Limbo)\n\n### 2015\n* [OpenTimer: A High-performance Timing Analysis Tool for VLSI Systems](https://github.com/OpenTimer/OpenTimer)\n* [Ophidian: Open-Source Library for Physical Design Research and Teaching.](https://gitlab.com/eclufsc/ophidian)\n* [OpenMPL](https://github.com/limbo018/OpenMPL)\n \n\n### 2016\n* [A Modeling and Verification Platform for SoCs using ILAs](https://github.com/Bo-Yuan-Huang/ILAng)\n* [Mixed Hardware/Software Emulation](https://github.com/Xilinx/systemctlm-cosim-demo)\n* [SystemC TLM Interfaces](https://github.com/Xilinx/libsystemctlm-soc)\n* [BoxRouter (Global Router)](https://github.com/krzhu/BoxRouter)\n\n### 2017\n* [Rsync](https://github.com/RsynTeam/rsyn-x)\n* [Cloud-V](https://github.com/Cloud-V)\n* [HAMMER:Highly Agile Masks Made Effortlessly from RTL](https://github.com/ucb-bar/hammer)\n* [Magic](https://github.com/libresilicon/magic-8.22017)\n* [GDS Viewer](https://github.com/KLayout/klayout)\n\n\n### 2018\n* [Lgraph: Live Graph infrastructure for Synthesis and Simulation](https://github.com/masc-ucsc/lgraph)\n* [OpenPiton](https://github.com/PrincetonUniversity/openpiton)\n* [Cpp-Taskflow](https://github.com/cpp-taskflow/cpp-taskflow)\n* [Parser-SPEF](https://github.com/OpenTimer/Parser-SPEF)\n* [DATCRobustDesignFlow](https://github.com/jinwookjungs/datc_robust_design_flow)\n* [EPFLLogicSynthesisLibraries](https://github.com/lsils/lstools-showcase?)\n* [OpenSTA](https://github.com/abk-openroad/OpenSTA)\n* [RePlace](https://github.com/abk-openroad/RePlAce)\n* [TritoCTS](https://github.com/abk-openroad/TritonCTS)\n* [TritonSizer](https://github.com/abk-openroad/TritonSizer)\n* [BSD-DME](https://github.com/abk-openroad/BST-DME\t)\n* [LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G](https://github.com/lewiz-support/LMAC_CORE2)\n* [LeWiz Communications, Inc. Ethernet MAC Core1 - Ethernet 1G/100M/10M](https://github.com/lewiz-support/LMAC_CORE1)\n* [12nm RAIL library](https://github.com/rail-posh/rail12)\n* [65nm RAIL Library](https://github.com/rail-posh/rail65)\n* [A framework for FPGA emulation of mixed-signal systems](https://github.com/sgherbst/anasymod)\n* [AXI Protocol Checker](https://github.com/upscale-project/case-studies/tree/master/axi)\n* [CoreIR Symbolic Analyzer](https://github.com/cristian-mattarei/CoSA)\n* [Open-source FPGA Workflow](https://github.com/PrincetonUniversity/prga)\n* [FPGA-SPICE](https://github.com/LNIS-Projects/OpenFPGA)\n* [Tools regarding on analog modeling, validation, and generation](https://github.com/StanfordVLSI/DaVE)\n* [OpenDP (Open Source Detailed Placement)](https://github.com/sanggido/OpenDP)\n* [University of Minnesota / Intel (Automated Analog Layout)](https://github.com/ALIGN-analoglayout/ALIGN-public)\n* [gds2Para (Complete Integrated Circuit (IC) Layout Analysis from GDSII Design File to Parasitics Extraction)](https://github.com/purdue-onchip/gds2Para)\n* [University of Utah (Logic Synthesis)](https://github.com/LNIS-Projects/LSOracle)\n* [JITX (Intent Driven Board Design)](https://github.com/JITx-Inc/darpa-idea)\n* [The EPFL Combinational Benchmark Suite](https://github.com/lsils/benchmarks)\n\n\n### 2019\n* [Analog Known Good Designs](https://github.com/USCPOSH/AMS_KGD)\n* [Analog Parameter Search Engine](https://github.com/USCPOSH/AMPSE)\n* [Brown (Open Source PVT Sensors)](https://github.com/scale-lab/PVTsensors)\n* [Circuit IP Sanitizer](https://github.com/USCPOSH/Sanitizer)\n* [Serial Link Mixed Signal Modeling](https://github.com/upscale-project/hslink_phy)\n* [UW-IDEA_AnalogTestCases](https://github.com/uwidea/UW-IDEA_AnalogTestCases)\n* [System Verilog to Verilog](https://github.com/umich-cadre/sv2v)\n* [Asynchronous Memory Compiler](https://github.com/asyncvlsi/AMC)\n* [University of Michigan (Intent Driven Analog Design)](https://github.com/idea-fasoc/datasheet-scrubber)\n* [Machine Generated Analog IC Layout](https://github.com/magical-eda/MAGICAL)\n* [Magical Test Circuits](https://github.com/magical-eda/MAGICAL-CIRCUITS)\n* [UW BSG Pipecleaner Suite](https://github.com/bespoke-silicon-group/bsg_pipeclean_suite)\n* [OpenPiton Design Benchmark](https://github.com/PrincetonUniversity/OPDB)\n* [System Verilog to Verilog](https://github.com/bespoke-silicon-group/bsg_sv2v)\n* [Utd-SystemVerilog](https://github.com/billswartz7/utd-SystemVerilog)\n\n\n## Summary\n\n| Year | Number | Cumulative Number |\n| :--- |  :---:  | :---: |\n| [1999](#1999) | 1  | 1 |    \n| [2002](#2002) | 1  | 2 | \n| [2004](#2004) | 1  | 3 | \n| [2005](#2005) | 1  | 4 | \n| [2009](#2009) | 1  | 5 | \n| [2010](#2010) | 1  | 6 | \n| [2011](#2011) | 1  | 7 | \n| [2012](#2012) | 3  | 10 | \n| [2013](#2013) | 1  | 11 | \n| [2014](#2014) | 2  | 13 | \n| [2015](#2015) | 3  | 16 | \n| [2016](#2016) | 4  | 20 | \n| [2017](#2017) | 5  | 25 | \n| [2018](#2018) | 28  | 53 | \n| [2019](#2019) | 15  | 68 | \n\n\n## Reference\n* T.-W. Huang, C.-X. Lin, G. Guo, and Martin D. F. Wong, [Essential Building Blocks for Creating an Open-source EDA Project][DAC19 paper], ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, 2019.\n* [Essential Building Blocks for Creating an Open-source EDA Project][DAC19 slides]. Invited talk at DAC.\n* [DARPA Intelligent Design of Electronic Assets (IDEA)][DARPA IDEA] \n* [DARPA Posh Open Source Hardware (POSH)][DARPA POSH]\n* [List of IDEA Projects][DARPA IDEA GitHub] \n* [List of POSH Projects][DARPA POSH GitHub]\n\n\n* * *\n\n[GitHub pull requests]:  https://github.com/clin99/awesome-eda/pulls\n[email me]:              mailto:twh760812@gmail.com \n[DAC19 slides]:          https://tsung-wei-huang.github.io/talk/dac19-invited.pdf \n[DAC19 paper]:           https://tsung-wei-huang.github.io/papers/dac19-invited.pdf\n[DARPA IDEA]:            https://www.darpa.mil/program/intelligent-design-of-electronic-assets  \n[DARPA POSH]:            https://www.darpa.mil/program/posh-open-source-hardware\n[DARPA IDEA GitHub]:     https://github.com/aolofsson/IDEA \n[DARPA POSH GitHub]:     https://github.com/aolofsson/POSH\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fclin99%2Fawesome-eda","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fclin99%2Fawesome-eda","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fclin99%2Fawesome-eda/lists"}