{"id":29032001,"url":"https://github.com/cnvogelg/captvolt-vcv","last_synced_at":"2025-08-17T20:09:50.968Z","repository":{"id":138277864,"uuid":"330264713","full_name":"cnvogelg/captvolt-vcv","owner":"cnvogelg","description":"captvolt Eurorack Modules for VCV","archived":false,"fork":false,"pushed_at":"2024-08-07T20:04:01.000Z","size":921,"stargazers_count":6,"open_issues_count":0,"forks_count":1,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-06-26T10:49:49.208Z","etag":null,"topics":["6581","8580","resid","sid","sidofon","vcv","vcvrack"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cnvogelg.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2021-01-16T21:50:27.000Z","updated_at":"2024-08-07T20:02:12.000Z","dependencies_parsed_at":null,"dependency_job_id":"08681c99-a14a-4d8a-8011-49a8f97383c7","html_url":"https://github.com/cnvogelg/captvolt-vcv","commit_stats":null,"previous_names":[],"tags_count":4,"template":false,"template_full_name":null,"purl":"pkg:github/cnvogelg/captvolt-vcv","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cnvogelg%2Fcaptvolt-vcv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cnvogelg%2Fcaptvolt-vcv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cnvogelg%2Fcaptvolt-vcv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cnvogelg%2Fcaptvolt-vcv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cnvogelg","download_url":"https://codeload.github.com/cnvogelg/captvolt-vcv/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cnvogelg%2Fcaptvolt-vcv/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":270899579,"owners_count":24664720,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-17T02:00:09.016Z","response_time":129,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["6581","8580","resid","sid","sidofon","vcv","vcvrack"],"created_at":"2025-06-26T10:30:26.169Z","updated_at":"2025-08-17T20:09:50.899Z","avatar_url":"https://github.com/cnvogelg.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# CaptVolt's VCV Modules\n\n## sidofon \n\n![module screenshot](./doc/sidofon.png)\n\nAdd Commodore 64's famous SID Chip (6581 or 8580) as a module to your VCV Rack.\n\nUsing Dag Lem's very accurate [ReSID][1] Emulation the module offers raw\naccess to all registers of the SID on bit level. Each parameter is mapped to\ncorresponding CV inputs. Additionally, manual controls are available.\n\nWe assume that you are familar with the SID's registers. If not the \n[SID 6581 data sheet][2] is a must read.\n\nBoth SID types 6581 and 8580 can be emulated. Select the desired type in the\nmodules menu.\n\n[1]: ./src/resid/README\n[2]: http://archive.6502.org/datasheets/mos_6581_sid.pdf\n\n### General Notes\n\nThe module's parameters can be either controlled manually by specific controls\nor via CV input. \n\nNote that always both the voltage derived from the control is added to the\nCV. So make sure to completely disable a manual control in order to have\nfull control via CV.\n\nFor toggle/switch like controls the module offers a DIP switch. For \ncontinous values a normal or trim pot is available.\n\nFor switches an input CV of \u003e= 1V enabled it. Range values are typically\nmapped from the unipolar (0-10V) CV range.\n\n### Register Clocking\n\nAs the SID digitally controls its parameters its update rate was not \ncontinuous or immediate but happened when the CPU was able to write the\nregisters of the SID.\n\nIn order to simulate this characteristic 8-bit sound generation this module\nalso does update the register values (here provided by CVs or manually) only\nin a given rate. The `Clk` input allows to feed in this update clock from\nan external source.\n\nIf no input clock is given then the module synthesizes its own clock available\non the `Clk` output. In most applications the SID registers were written in\nregular intervals e.g. based on the vertical refresh rate. The generated clock\nis also based on either 50 Hz (PAL) or 60 Hz (NTSC) depending on the\ntelevision norm of your county. It also allows to oversample this clock by\na fixed factor to achieve higher update rates.\n\nThe module menu allows to configure the internal clock settings.\n\nEach CV input has a small LED that shows its current value: either off or \nincreasing values with increasing brightness. This LEDs are updated when\nthe internal registers of the SID are updated and thus visualize the \nupdate rate.\n\n### Voice Section\n\nFor each of the SID's 3 Voices a voice section is available in the module with\nthe following parameters:\n\n#### Pitch\n\nOscillator Pitch mapps 1V/Oct input signal to the `FreqHi/FreqLo` register.\n\n#### PW\n\nMaps a bipolar CV to the pulse width of the rectangle waveform. 0V is 50%,\n\u003c=-1V is 0%, and \u003e=1V is 100% duty cycle\n\n#### Waveform\n\nSelect one or multiple waveforms for the voice by manually toggling the\nDIP switches or by applying a switch CV of \u003e= 1V.\n\nThe `Tri`, `Saw`, `Pulse`, and `Noise` CVs set the corresponding waveform\nbit for this voice.\n\n#### Control Bits\n\n`Gate`, `Sync`, `RingMod`, and `Test` directly map to the bits 0 to 3 in the\nvoice control register.\n\n#### ADSR\n\nThe ADSR values are converted to the discrete (0-15 range) values in the\nSID registers. The full unipolar range 0-10V of a CV is mapped.\n\n#### Voice 3 Oscillator and Envelope Output\n\nVoice 3 of the SID offers a special feature: `Osc` outputs the current\noscillator signal as a bipolar CV. `Env` outputs the envelope as a unipolar\nCV. Both outputs are actual 8 bit register reads of the chip and therefore\nquantized signals. By disabling voice 3 (see `3Off`) you could use voice 3\nas a modulation source for your patch.\n\n### Filter Section\n\n#### Filter Cut Off\n\nControl the cut off frequency in the `FC low/high` register of the SID.\nThe unipolar range of the CV (0-10V) is mapped to the discrete range\n0-2047.\n\n#### Filter Resonance\n\nAdjust the filter resonance value. The unipolar range of the CV (0-10V)\nis mapped to the discrete range 0-15 in the SID register.\n\n#### Main Volume\n\nAdjust the main output volume of the SID chip. The unipolar range of the CV\n(0-10V) is mapped to the discrete range 0-15 in the SID register.\n\n#### Filter Voice 1-3, Aux\n\nThese switches allow to control which voice is affected by the filter.\nAdditionally, you can also filter an external audio stream fed in via\nthe `Aux` input.\n\n#### Filter Mode: LP, BP, HP\n\nSelect the filter operation mode: Low-pass, band-pass, or high-pass.\nUse the `Mode` DIP switches to manually select the filter.\nCVs are switch like (\u003e=1V is on).\n\n#### Disable Voice 3: 3Off\n\nA switch controlling the `3Off` bit in the `Mode/Vol` register of the SID.\n\n### I/O Section\n\nInput `Clk` allows to feed in the register update clock via an external source.\n\nInput `Aux` feeds in an external audio stream for filtering\n\nOutput `Clk` either replicates the input `Clk` if connected or outputs a\nsynthesized vertical refresh clock of 50Hz or 60Hz with optional oversampling.\n\nOutput `Out` outputs the mixed audio signal of the SID chip containing\nall three voices and the aux input. All are passed either dry or filtered.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcnvogelg%2Fcaptvolt-vcv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcnvogelg%2Fcaptvolt-vcv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcnvogelg%2Fcaptvolt-vcv/lists"}