{"id":27438326,"url":"https://github.com/comidan/simplehardwarenavigator","last_synced_at":"2026-02-02T03:02:44.906Z","repository":{"id":91783385,"uuid":"223475570","full_name":"comidan/SimpleHardwareNavigator","owner":"comidan","description":"Simple navigator entirely relying on its own hardware built with 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SimpleHardwareNavigator\nSimple navigator entirely relying on its own hardware built with VHDL.\n\nIt was used a FPGA xc7a200tfbg484-1 with a clock of 100ns.\n\n```\nentity project_logic_net is\nport (\n    i_clk : in std_logic;\n    i_start : in std_logic;\n    i_rst : in std_logic;\n    i_data : in std_logic_vector(7 downto 0);\n    o_address : out std_logic_vector(15 downto 0);\n    o_done : out std_logic;\n    o_en : out std_logic;\n    o_we : out std_logic;\n    o_data : out std_logic_vector (7 downto 0)\n);\nend project_logic_net;\n```\nIn particular:  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● i_clk it's the clock signal  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● i_start it's the start of computation signal  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● i_rst it's the RESET signal which allow the component to reeive a START signal  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● i_data it's the signal coming from the RAM in a form of a vector after a RAM read request  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● o_address it's the vector signal for telling the RAM which address I want to read from  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● o_done it's the signal of the end of the computation  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● o_en it's the ENABLE signal for allowing communication with RAM, needed for both writes and reads  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● o_we it's the WRITE ENABLE signal which if equal to 1 can write, otherwise 0 to read  \n\u0026nbsp;\u0026nbsp;\u0026nbsp;● o_data it's the vector signal sent to the RAM which will be written at the requested address  \n\nRAM description\n```\nlibrary ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\nentity rams_sp_wf is\nport(\n    clk : in std_logic;\n    we : in std_logic;\n    en : in std_logic;\n    addr : in std_logic_vector(15 downto 0);\n    di : in std_logic_vector(7 downto 0);\n    do : out std_logic_vector(7 downto 0)\n);\nend rams_sp_wf;\narchitecture syn of rams_sp_wf is\ntype ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0);\nsignal RAM : ram_type;\nbegin\n    process(clk)\n    begin\n        if clk'event and clk = '1' then\n            if en = '1' then\n                if we = '1' then\n                    RAM(conv_integer(addr)) \u003c= di;\n                    do \u003c= di;\n                else\n                    do \u003c= RAM(conv_integer(addr));\n                end if;\n            end if;\n        end if;\n    end process;\nend syn;\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcomidan%2Fsimplehardwarenavigator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcomidan%2Fsimplehardwarenavigator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcomidan%2Fsimplehardwarenavigator/lists"}