{"id":49141428,"url":"https://github.com/cornell-zhang/eqmap","last_synced_at":"2026-04-22T01:04:44.493Z","repository":{"id":305060644,"uuid":"873909989","full_name":"cornell-zhang/eqmap","owner":"cornell-zhang","description":"Using e-graphs for logic synthesis (ICCAD'25)","archived":false,"fork":false,"pushed_at":"2026-04-21T15:13:38.000Z","size":4131,"stargazers_count":33,"open_issues_count":8,"forks_count":4,"subscribers_count":2,"default_branch":"main","last_synced_at":"2026-04-21T17:17:00.300Z","etag":null,"topics":["compiler","egg","fpga","rtl","rust","synthesis","verilog","yosys"],"latest_commit_sha":null,"homepage":"","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cornell-zhang.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-10-16T23:48:27.000Z","updated_at":"2026-03-18T19:39:06.000Z","dependencies_parsed_at":"2025-07-18T06:02:05.859Z","dependency_job_id":"ec7a0895-c925-4ad2-a94d-54c823708295","html_url":"https://github.com/cornell-zhang/eqmap","commit_stats":null,"previous_names":["cornell-zhang/eqmap"],"tags_count":20,"template":false,"template_full_name":null,"purl":"pkg:github/cornell-zhang/eqmap","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cornell-zhang%2Feqmap","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cornell-zhang%2Feqmap/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cornell-zhang%2Feqmap/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cornell-zhang%2Feqmap/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cornell-zhang","download_url":"https://codeload.github.com/cornell-zhang/eqmap/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cornell-zhang%2Feqmap/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":32116514,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-22T00:31:26.853Z","status":"ssl_error","status_checked_at":"2026-04-22T00:30:22.894Z","response_time":128,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["compiler","egg","fpga","rtl","rust","synthesis","verilog","yosys"],"created_at":"2026-04-22T01:04:43.870Z","updated_at":"2026-04-22T01:04:44.486Z","avatar_url":"https://github.com/cornell-zhang.png","language":"Rust","funding_links":[],"categories":[],"sub_categories":[],"readme":"![](https://github.com/cornell-zhang/eqmap/actions/workflows/rust.yml/badge.svg)\n[![Docs](https://img.shields.io/badge/docs-github--pages-blue)](https://cornell-zhang.github.io/eqmap/)\n\n# EqMap: FPGA LUT Technology Mapping w/ E-Graphs\n\nEqMap is Verilog-to-Verilog tool that attempts to superoptimize FPGA technology mapping using E-Graphs. Our experiments show that equality saturation techniques can improve cut selection and ultimately produce smaller circuits than the commercial tools.\n\nYou might also want to check out the [docs](https://cornell-zhang.github.io/eqmap/) or the [ICCAD publication](https://github.com/cornell-zhang/eqmap/blob/main/eqmap_iccad.pdf).\n\n## Getting Started\n\n### Dependencies for Users\n\n- [rustup](https://rustup.rs/)\n  - Crates (fetched automatically)\n    - [egg](https://docs.rs/egg/latest/egg/), [safety-net](https://docs.rs/safety-net/latest/safety_net/), [good_lp](https://docs.rs/good_lp/latest/good_lp/), [bitvec](https://docs.rs/bitvec/latest/bitvec/), [clap](https://docs.rs/clap/latest/clap/), [indicatif](https://docs.rs/indicatif/latest/indicatif/), [sv-parser](https://docs.rs/sv-parser/latest/sv_parser/), [serde_json](https://docs.rs/serde_json/latest/serde_json/)\n- [Yosys 0.33](https://github.com/YosysHQ/yosys/releases/tag/yosys-0.33)\n- *Optional* [CBC Solver](https://github.com/coin-or/Cbc)\n\n### Dependencies for Devs\n\n- VSCode Extensions\n  - [Rust Analyzer Extension](https://rust-analyzer.github.io/)\n  - [VerilogHDL Extension](https://marketplace.visualstudio.com/items?itemName=mshr-h.VerilogHDL)\n- RTL Tools\n  - [Verilator](https://github.com/verilator/verilator)\n  - [Verible](https://github.com/chipsalliance/verible)\n\n### Building the Tools\n\nFirst, check the prerequisites for building. For basic functionality, you will need the Rust toolchain and a Yosys 0.33 install. Linux is preferred, but MacOS and WSL should work without much trouble.\n\n`cargo build`\n\n`cargo run --release -- tests/verilog/mux_reg.v # Sanity check`\n\n### Bring Your Own RTL\n\nYou can also try to synthesize your own verilog module `my_file.v`, but it must confirm to a strict subset of Verilog. For example, the module must have a flat hierarchy and all top-level ports must be 1 bit signals.\n\n`source utils/setup.sh # Add eqmap script to PATH`\n\n`eqmap my_file.v`\n\nUse `--help` to get an overview of all the options the compiler has:\n\n```\n$ eqmap --help\nTechnology Mapping Optimization with E-Graphs\n\nUsage: eqmap_fpga [OPTIONS] [INPUT] [OUTPUT]\n\nArguments:\n  [INPUT]   Verilog file to read from (or use stdin)\n  [OUTPUT]  Verilog file to output to (or use stdout)\n\nOptions:\n      --report \u003cREPORT\u003e            If provided, output a JSON file with result data\n  -a, --assert-sat                 Return an error if the graph does not reach saturation\n  -f, --no-verify                  Do not verify the functionality of the output\n  -c, --no-canonicalize            Do not canonicalize the input into LUTs\n  -d, --decomp                     Find new decompositions at runtime\n      --disassemble \u003cDISASSEMBLE\u003e  Comma separated list of cell types to decompose into\n  -r, --no-retime                  Do not use register retiming\n  -v, --verbose                    Print explanations (generates a proof and runs slower)\n      --min-depth                  Extract for minimum circuit depth\n  -k, --k \u003cK\u003e                      Max fan in size allowed for extracted LUTs\n  -w, --reg-weight \u003cREG_WEIGHT\u003e    Ratio of register cost to LUT cost\n  -t, --timeout \u003cTIMEOUT\u003e          Build/extraction timeout in seconds\n  -s, --node-limit \u003cNODE_LIMIT\u003e    Maximum number of nodes in graph\n  -n, --iter-limit \u003cITER_LIMIT\u003e    Maximum number of rewrite iterations\n  -h, --help                       Print help\n  -V, --version                    Print version\n```\n\nYou will likely want to use the `--report \u003cfile\u003e` flag to measure improvements in LUT count and circuit depth. You can also try compiling with the `exact_highs` feature, which will enable `--exact highs` as a EqMap flag.\n\n### Features\n\nThe project has three conditionally compiled features:\n\n1. `egraph_fold` (deprecated)\n2. `exact_cbc` (used for ILP exact synthesis, requires [CBC](https://github.com/coin-or/Cbc))\n3. `exact_highs` (used for ILP exact synthesis, using HiGHS)\n4. `cut_analysis` (on by default)\n5. `graph_dumps` (enables the serialization module and `--dump-graph` argument)\n\nTo build with any of these features enabled:\n\n`source utils/setup.sh \u003cfeature\u003e`\n\n### Docs\n\nYou can generate most of the documentation with `cargo doc`.\n\n### Citation\n\n```bibtex\n @inproceedings{11240672,\n  author    = {Hofmann, Matthew and Gokmen, Berk and Zhang, Zhiru},\n  booktitle = {2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD)},\n  title     = {EqMap: FPGA LUT Remapping using E-Graphs},\n  year      = {2025},\n  volume    = {},\n  number    = {},\n  pages     = {1-9},\n  keywords  = {Runtime;Design automation;Heuristic algorithms;Circuits;Table lookup;Computational complexity;Field programmable gate arrays},\n  doi       = {10.1109/ICCAD66269.2025.11240672}\n}\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcornell-zhang%2Feqmap","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcornell-zhang%2Feqmap","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcornell-zhang%2Feqmap/lists"}