{"id":13575806,"url":"https://github.com/corsix/amx","last_synced_at":"2026-03-13T01:37:25.285Z","repository":{"id":58498003,"uuid":"530536922","full_name":"corsix/amx","owner":"corsix","description":"Apple AMX Instruction Set","archived":false,"fork":false,"pushed_at":"2024-12-26T15:29:28.000Z","size":199,"stargazers_count":1063,"open_issues_count":2,"forks_count":52,"subscribers_count":27,"default_branch":"main","last_synced_at":"2025-04-04T23:33:47.336Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/corsix.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-08-30T07:02:17.000Z","updated_at":"2025-04-02T15:51:11.000Z","dependencies_parsed_at":"2024-03-01T12:25:53.498Z","dependency_job_id":"21b15c0d-ea45-45bc-b595-68414d745dfe","html_url":"https://github.com/corsix/amx","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/corsix/amx","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/corsix%2Famx","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/corsix%2Famx/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/corsix%2Famx/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/corsix%2Famx/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/corsix","download_url":"https://codeload.github.com/corsix/amx/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/corsix%2Famx/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30454006,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-12T21:31:01.033Z","status":"ssl_error","status_checked_at":"2026-03-12T21:30:43.161Z","response_time":114,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T15:01:04.385Z","updated_at":"2026-03-13T01:37:25.256Z","avatar_url":"https://github.com/corsix.png","language":"C","funding_links":[],"categories":["Hardware","C"],"sub_categories":["CPU"],"readme":"Contemporary M1 / M2 / M3 / M4 machines from Apple have (at least) four different ways for low-level programmers to perform heavy computations:\n1. Standard ARMv8 SIMD/NEON vector instructions on CPU cores (128 bits wide, issue [up to four per cycle on Firestorm](https://dougallj.github.io/applecpu/firestorm-simd.html))\n2. Apple's undocumented AMX instructions, issued from CPU, executed on a special accelerator execution unit\n3. The Neural Engine (called ANE or NPU)\n4. The GPU (e.g. [Metal Compute Shaders](https://developer.apple.com/documentation/metal/performing_calculations_on_a_gpu))\n\nThis repository is all about the 2\u003csup\u003end\u003c/sup\u003e of those: Apple's AMX instructions. Note that these instructions are neither documented nor supported by Apple. As a source of potential great confusion, Apple's AMX instructions are completely distinct from [Intel's AMX instructions](https://en.wikipedia.org/wiki/Advanced_Matrix_Extensions), though both are intended for issuing matrix multiply operations from a CPU.\n\nThe research was done on an Apple M1 Max (2021), with follow-up work on an M2 (2023), and additional follow-up work on an M3 (2023) and M4 Max (2024). Older or newer chips might have different AMX instructions. [Some sources](https://nod.ai/comparing-apple-m1-with-amx2-m1-with-neon/) report that the M1 contains version 2 of the AMX instructions, which seems plausible (possibly everything using 7-bit writemasks comes from version 1, and everything using 9-bit writemasks is new in version 2). The M1 to M2 transition [adds bf16 support, along with a few other tweaks](https://github.com/corsix/amx/issues/5#issuecomment-1464639729). The M2 to M3 transition [adds one extra mode to each of `ldx` and `ldy` and `matint`](https://github.com/corsix/amx/issues/10). The M3 to M4 transition [causes some modes of `extrh`, `extrv`, `vecfp`, and `vecint` to ignore low bits of X/Y offset](https://github.com/corsix/amx/issues/13).\n\nA good one-image summary of AMX is the following figure from [abandoned patent US20180074824A1](https://patents.google.com/patent/US20180074824A1/en). Consider a 32x32 grid of compute units, where each unit can perform 16-bit multiply-accumulate, or a 2x2 subgrid of units can perform 32-bit multiply-accumulate, or a 4x4 subgrid can perform 64-bit multiply-accumulate. To feed this grid, there is a pool of X registers each containing 32 16-bit elements (or 16 32-bit elements, or 8 64-bit elements) and a pool of Y registers similarly containing 32 16-bit elements (or 16 32-bit elements, or 8 64-bit elements). A single instruction can perform a full outer product: multiply every element of an X register with every element of a Y register, and accumulate with the Z element in the corresponding position.\n\n![US20180074824A1 Figure 2](fig2.png)\n\nA single row of the 32x32 grid can also be used to perform vector operations (rather than matrix operations) between X and Y\u003csup\u003eT\u003c/sup\u003e.\n\nIn terms of available data types, the general pattern is:\n- IEEE754 f16 or f32 or f64 (same width for all three fused-multiply-add operands)\n- IEEE754 f16 multiplicands, accumulating onto f32\n- On M2 hardware, bf16 multiplicands, accumulating onto bf16 or IEEE754 f32\n- Integer 8-bit or 16-bit multiplicands, accumulating onto 16 or 32 bits (in various signednesses)\n\nThis repository provides:\n- [A tiny header for accessing AMX instructions](aarch64.h) (use at your own risk)\n- [A description of the register file](RegisterFile.md)\n- [A full description of every instruction](Instructions.md)\n- [C code matching the behaviour of every instruction](test.md) (using inline ARMv8 assembly to express certain things)\n- [References for further reading](References.md)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcorsix%2Famx","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcorsix%2Famx","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcorsix%2Famx/lists"}