{"id":17046436,"url":"https://github.com/cpldcpu/llm_hdl_design","last_synced_at":"2025-04-12T15:34:21.456Z","repository":{"id":168383021,"uuid":"644043839","full_name":"cpldcpu/LLM_HDL_Design","owner":"cpldcpu","description":"Some hardware design experiments using large language models","archived":false,"fork":false,"pushed_at":"2025-03-01T16:20:54.000Z","size":114,"stargazers_count":5,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-26T10:05:09.733Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cpldcpu.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-05-22T17:34:35.000Z","updated_at":"2025-03-01T16:20:58.000Z","dependencies_parsed_at":"2023-06-14T15:00:42.021Z","dependency_job_id":"7d9e7b28-139b-447f-aff7-aeb54c1ffce8","html_url":"https://github.com/cpldcpu/LLM_HDL_Design","commit_stats":null,"previous_names":["cpldcpu/llm_hdl_design"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FLLM_HDL_Design","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FLLM_HDL_Design/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FLLM_HDL_Design/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FLLM_HDL_Design/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cpldcpu","download_url":"https://codeload.github.com/cpldcpu/LLM_HDL_Design/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248589950,"owners_count":21129710,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-14T09:46:16.723Z","updated_at":"2025-04-12T15:34:21.448Z","avatar_url":"https://github.com/cpldcpu.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# LLM_HDL_Design\nSome hardware design experiments using large language models\n\nThis repo is mostly interesting for its history. I tracked\nthe ability of LLMs to generate a simple CPU core in Verilog\nstarting in early 2023. Once Sonnet 3.5 was released in \nJune 2024, it was able to one-shot everything so that it\ndid not make sense to continue and further.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcpldcpu%2Fllm_hdl_design","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcpldcpu%2Fllm_hdl_design","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcpldcpu%2Fllm_hdl_design/lists"}