{"id":17046452,"url":"https://github.com/cpldcpu/tinytapeout_trainled","last_synced_at":"2026-03-18T23:15:17.848Z","repository":{"id":70757082,"uuid":"531676153","full_name":"cpldcpu/TinyTapeout_TrainLED","owner":"cpldcpu","description":null,"archived":false,"fork":false,"pushed_at":"2022-09-22T14:06:02.000Z","size":20,"stargazers_count":0,"open_issues_count":1,"forks_count":1,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-01-28T09:44:39.889Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cpldcpu.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null},"funding":{"custom":["https://zerotoasiccourse.com"]}},"created_at":"2022-09-01T20:28:18.000Z","updated_at":"2022-09-01T20:28:23.000Z","dependencies_parsed_at":"2023-09-14T14:34:32.853Z","dependency_job_id":null,"html_url":"https://github.com/cpldcpu/TinyTapeout_TrainLED","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":"mattvenn/wokwi-verilog-gds-test","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FTinyTapeout_TrainLED","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FTinyTapeout_TrainLED/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FTinyTapeout_TrainLED/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cpldcpu%2FTinyTapeout_TrainLED/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cpldcpu","download_url":"https://codeload.github.com/cpldcpu/TinyTapeout_TrainLED/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":245049318,"owners_count":20552666,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-14T09:46:18.201Z","updated_at":"2026-01-05T03:50:20.841Z","avatar_url":"https://github.com/cpldcpu.png","language":"Verilog","funding_links":["https://zerotoasiccourse.com"],"categories":[],"sub_categories":[],"readme":"![](../../workflows/wokwi/badge.svg)\n\nLast minute contribution to TinyTapeout developed life in a Train.\nThis is a PWM RGB LED driver that is programmed using a serial protocol similar to WS2812.\n\noriginal readme\n-----\nGo to https://tinytapeout.com for instructions!\n\n# How to change the Wokwi project\n\nEdit the [Makefile](Makefile) and change the WOKWI_PROJECT_ID to match your project.\n\n# What is this about?\n\nThis repo is a template you can make a copy of for your own [ASIC](https://www.zerotoasiccourse.com/terminology/asic/) design using [Wokwi](https://wokwi.com/).\n\nWhen you edit the Makefile to choose a different ID, the [GitHub Action](.github/workflows/wokwi.yaml) will fetch the digital netlist of your design from Wokwi.\n\nThe design gets wrapped in some extra logic that builds a 'scan chain'. This is a way to put lots of designs onto one chip and still have access to them all. You can see [all of the technical details here](https://github.com/mattvenn/scan_wrapper).\n\nAfter that, the action uses the open source ASIC tool called [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/) to build the files needed to fabricate an ASIC.\n\n# What files get made?\n\nWhen the action is complete, you can [click here](https://github.com/mattvenn/wokwi-verilog-gds-test/actions) to see the latest build of your design. You need to download the zip file and take a look at the contents:\n\n* gds_render.svg - picture of your ASIC design\n* gds.html - zoomable picture of your ASIC design\n* runs/wokwi/reports/final_summary_report.csv  - CSV file with lots of details about the design\n* runs/wokwi/reports/synthesis/1-synthesis.stat.rpt.strategy4 - list of the [standard cells](https://www.zerotoasiccourse.com/terminology/standardcell/) used by your design\n* runs/wokwi/results/final/gds/user_module.gds - the final [GDS](https://www.zerotoasiccourse.com/terminology/gds2/) file needed to make your design\n\n# What next?\n\n* Share your GDS on twitter, tag it #tinytapeout and [link me](https://twitter.com/matthewvenn)!\n* [Submit it to be made](https://docs.google.com/forms/d/e/1FAIpQLSc3ZF0AHKD3LoZRSmKX5byl-0AzrSK8ADeh0DtkZQX0bbr16w/viewform?usp=sf_link)\n* [Join the community](https://discord.gg/rPK2nSjxy8)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcpldcpu%2Ftinytapeout_trainled","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcpldcpu%2Ftinytapeout_trainled","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcpldcpu%2Ftinytapeout_trainled/lists"}