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following command:\n\n\n    $ pip3 install pyverilator\n\n\nUsage\n-----\n\nAssume you have the following verilog module stored in ``counter.v``.\n\n.. code:: verilog\n\n    module counter (\n            input        clk,\n            input        rst,\n            input        en,\n            output [7:0] out\n        );\n        reg [7:0] count_reg;\n        wire [7:0] next_count_reg;\n        assign next_count_reg = (en == 1) ? count_reg + 1 : count_reg;\n        assign out = next_count_reg;\n        always @(posedge clk) begin\n            if (rst == 1) count_reg \u003c= 0;\n            else          count_reg \u003c= next_count_reg;\n        end\n    endmodule'''\n\nThen you can use ``pyverilator`` to simulate this module using verilator in\npython.\n\n.. code:: python\n\n    sim = pyverilator.PyVerilator.build('counter.v')\n\n    # start gtkwave to view the waveforms as they are made\n    sim.start_gtkwave()\n\n    # add all the io and internal signals to gtkwave\n    sim.send_signals_to_gtkwave(sim.io)\n    sim.send_signals_to_gtkwave(sim.internals)\n\n    # add all the io and internal signals to gtkwave\n    sim.send_to_gtkwave(sim.io)\n    sim.send_to_gtkwave(sim.internals)\n\n    # tick the automatically detected clock\n    sim.clock.tick()\n\n    # set rst back to 0\n    sim.io.rst = 0\n\n    # check out when en = 0\n    sim.io.en = 0\n    curr_out = sim.io.out\n    # sim.io is a pyverilator.Collection, accessing signals by attribute or\n    # dictionary syntax returns a SignalValue object which inherits from int.\n    # sim.io.out can be used just like an int in most cases, and it has extra\n    # features like being able to add it to gtkwave with\n    # sim.io.out.send_to_gtkwave(). To just get the int value, you can call\n    # sim.io.out.value\n    print('sim.io.out = ' + str(curr_out))\n\n    # check out when en = 1\n    sim.io.en = 1\n    curr_out = sim.io.out\n    print('sim.io.out = ' + str(curr_out))\n\n    sim.clock.tick()\n\n    # check out after ticking clock\n    curr_out = sim.io.out\n    print('sim.io.out = ' + str(curr_out))\n\nThe full code for this and other examples can be found in the examples folder\nof the git repository.\n\nInstalling for Development\n--------------------------\n\nTo install this package for development, you should use a virtual environment,\nand install the package in editable mode using pip.\n\nTo create a virtual environment for this project, run the command below.\n\n    $ python3 -m venv path/to/new-venv-folder\n\nTo start using your new virtual environment, run the command below.\nThis needs to be run each time you open a new terminal.\n\n    $ source path/to/new-venv-folder/bin/activate\n\nAt this point you are now using your new virtual environment.\nPython packages you install in this environment will not be available outside\nyour virtual environment.\nIf you want to stop using the virtual environment, just run ``deactivate``.\n\nTo install the ``pyverilator`` package in editable mode, inside the\n``pyverilator`` top git repository folder, run the command below.\n\n    $ pip3 install -e .\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcsail-csg%2Fpyverilator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcsail-csg%2Fpyverilator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcsail-csg%2Fpyverilator/lists"}