{"id":25131928,"url":"https://github.com/csgn/assembler","last_synced_at":"2026-05-18T04:11:59.702Z","repository":{"id":51366891,"uuid":"355230364","full_name":"csgn/Assembler","owner":"csgn","description":"Simple VM simulation","archived":false,"fork":false,"pushed_at":"2021-05-18T09:54:42.000Z","size":3415,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-04-03T00:11:34.897Z","etag":null,"topics":["0","assembler"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":false,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/csgn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2021-04-06T15:01:18.000Z","updated_at":"2025-01-16T10:45:51.000Z","dependencies_parsed_at":"2022-09-05T18:01:51.526Z","dependency_job_id":null,"html_url":"https://github.com/csgn/Assembler","commit_stats":null,"previous_names":[],"tags_count":11,"template":false,"template_full_name":null,"purl":"pkg:github/csgn/Assembler","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/csgn%2FAssembler","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/csgn%2FAssembler/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/csgn%2FAssembler/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/csgn%2FAssembler/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/csgn","download_url":"https://codeload.github.com/csgn/Assembler/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/csgn%2FAssembler/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":279017453,"owners_count":26086081,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-13T02:00:06.723Z","response_time":61,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["0","assembler"],"created_at":"2025-02-08T14:15:47.591Z","updated_at":"2025-10-14T01:15:38.019Z","avatar_url":"https://github.com/csgn.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003cdiv align=\"center\"\u003e\u003ch1\u003eAssembler\u003c/h1\u003e\n\n[![CMake](https://github.com/csergen/Assembler/actions/workflows/cmake.yml/badge.svg?branch=main)](https://github.com/csergen/Assembler/actions/workflows/cmake.yml)\n[![Codacy Badge](https://app.codacy.com/project/badge/Grade/a0630c3f393d44f0be60b17416025324)](https://www.codacy.com/gh/csergen/Assembler/dashboard?utm_source=github.com\u0026amp;utm_medium=referral\u0026amp;utm_content=csergen/Assembler\u0026amp;utm_campaign=Badge_Grade)\n[![csergen](https://circleci.com/gh/csergen/Assembler.svg?style=svg)](https://app.circleci.com/pipelines/github/csergen/Assembler?invite=true)\n\n*`std version: 11`* *`gcc: 11.1.1`*\n| Platform | Version | Status |\n| --- | --- | --- |\n|![Fedora Badge](https://img.shields.io/badge/Fedora-294172?style=for-the-badge\u0026logo=fedora\u0026logoColor=white)    |`33, 34` `64 bit`   | `PASSED ✅`|\n|![Ubuntu Badge](https://img.shields.io/badge/Ubuntu-E95420?style=for-the-badge\u0026logo=ubuntu\u0026logoColor=white)    |`18.04 LTS` `64 bit`| `PASSED ✅`|\n|![Windows Badge](https://img.shields.io/badge/Windows-0078D6?style=for-the-badge\u0026logo=windows\u0026logoColor=white) |`10` `64 bit`       | `PASSED ✅`|\n\n![flow](docs/img/flow.png)\n\u003c/div\u003e\n\n# **Getting Started**\n## Build with make ( **`version 4.3`** )\n```console\n$ make\n$ make clean\n```\n\n## Build with ![cmake badge](https://img.shields.io/badge/CMake-%23008FBA.svg?\u0026style=for-the-badge\u0026logo=cmake\u0026logoColor=white) ( **`version 3.19.7`** )\n```console\n    for linux\n$ cmake -S . -B build/ -DCMAKE_BUILD_TYPE=Debug\n\n    for windows\n$ cmake -S . -B build/ -A x64 -G \"Visual Studio 16 2019\"\n\n$ cmake --build build/ --config Debug\n$ ./build/Assembler \u003csource_file_path\u003e\n\n```\n## Build with ![docker badge](https://img.shields.io/badge/docker-%230db7ed.svg?\u0026style=for-the-badge\u0026logo=docker\u0026logoColor=white) ( **`version 20.10.6`** )\n```xml\n$ sudo systemctl start docker\n$ sudo docker build -t \u003ccustom_image_name\u003e \u003cdockerfile_path\u003e\n$ sudo docker run -it --rm --name \u003ccustom_container_name\u003e \u003ccustom_image_name\u003e\n```\n\n# Style Guide\n\n### Code Definition\n```assembly\nOPCODE REGISTER,[REGISTER, MEMORY, IMMEDIATE]\n\n# example\nHRK AX, BX\n    or\nHRK AX, [\u003cvariable_name\u003e]\n    or\nHRK AX, 10\n```\n\n### Variable Definition\n```assembly\n\u003cvariable_name\u003e: \u003cimmediate\u003e\n\n# example\nvar1: 10\n    or\nvar1: -10\n```\n\n### Branching\n```assembly\n\n\u003cLABEL\u003e: \u003cNEWLINE\u003e\n    something\n    \u003cBRANCHING_OPCODE\u003e \u003cLABEL\u003e\n\n# example\nLOP:\n    TOP AX, 10\n    SS LOP\n```\n\n# Grammar ( ebnf )\n```yaml\nprogram = field, { field };\n\nfield \n= [label],\n  [variable],\n  opcode, [register | memory_addressing | immediate]\n  [',', (register | memory_addressing | immediate)] newline\n\nlabel \n= STRING ':' newline;\n\nvariable\n= STRING ':' immediate;\n\nopcode\n=  HRK\n  |TOP\n  |CIK\n  |CRP\n  |BOL\n  |DEG\n  |VE\n  |VEYA\n  |SS\n  |SSD\n  |SN\n  |SP;\n\nregister \n=  AX\n  |BX\n  |CX\n  |DX;\n\nmemory_addressing\n= '[', ADDRESS, ']';\n\nimmediate\n= { decimal };\n\n\ndecimal = { -128 ... +127 };\n\nnewline = { [\\n] | [\\r\\n] };\n```\n\n\n# EXAMPLES\n\n### Factorial\n![factorial](docs/img/factorial.gif)\n\n```assembly\nRN: 5\n\nHRK AX, [RN]\nHRK CX, AX\n\nFACT: \n      CIK AX, 1\n      SS END\n      CRP CX, AX\n      SP FACT\n\nEND:\n```\n\n### Fibonacci\n![fibonacci](docs/img/fibonacci.gif)\n\n```assembly\nx1: 1\nx2: 1\n\nHRK AX, [x1]\nHRK BX, [x2]\n\nFIB:\n  HRK CX, AX\n  TOP AX, BX\n  HRK DX, AX\n  HRK BX, CX\n  HRK AX, DX\n  SP FIB\n```\n\n### Counter Example\n![ex](docs/img/ex.gif)\n\n```assembly\nco: 1\n\nHRK AX, 10\nHRK BX, 0\n\nHRK CX, AX\nDEG CX\nTOP CX, 1\n\nLOP:\n  TOP BX, [co]\n  TOP CX, [co]\n  SSD LOP\n  SS DEC\n\nDEC:\n  CIK BX, [co]\n  SP DEC\n```\n\n# DEFINITIONS\n\n### OPCODES\n```\nhrk   0000    0\ntop   0001    1\ncrp   0010    2\ncik   0011    3\nbol   0100    4\nve    0101    5\nveya  0110    6\ndeg   0111    7\nss    1000    8\nssd   1001    9\nsn    1010    A\nsp    1011    B\n```\n\n\n### REGISTERS\n```\nax  00  0\nbx  01  1\ncx  10  2\ndx  11  3\n```\n\n### ADDRESSING MODE\n```\njumping     00  0\nregister    01  1\nmemory      10  2\nimmediate   11  3\n```\n\n### INSTRUCTION TABLE\n\n#### HRK\n```assembly\nhrk reg(ax), reg(?)     0000 00 01  01\nhrk reg(bx), reg(?)     0000 01 01  05\nhrk reg(cx), reg(?)     0000 10 01  09\nhrk reg(dx), reg(?)     0000 11 01  0D\n\nhrk reg(ax), memory     0000 00 10  02\nhrk reg(bx), memory     0000 01 10  06\nhrk reg(cx), memory     0000 10 10  0A\nhrk reg(dx), memory     0000 11 10  0E\n\nhrk reg(ax), immediate  0000 00 11  03\nhrk reg(bx), immediate  0000 01 11  07\nhrk reg(cx), immediate  0000 10 11  0B\nhrk reg(dx), immediate  0000 11 11  0F\n```\n\n#### TOP\n```assembly\ntop reg(ax), reg(?)     0001 00 01  11\ntop reg(bx), reg(?)     0001 01 01  15\ntop reg(cx), reg(?)     0001 10 01  19\ntop reg(dx), reg(?)     0001 11 01  1D\n\ntop reg(ax), memory     0001 00 10  12\ntop reg(bx), memory     0001 01 10  16\ntop reg(cx), memory     0001 10 10  1A\ntop reg(dx), memory     0001 11 10  1E\n\ntop reg(ax), immediate  0001 00 11  13\ntop reg(bx), immediate  0001 01 11  17\ntop reg(cx), immediate  0001 10 11  1B\ntop reg(dx), immediate  0001 11 11  1F\n```\n\n#### CRP\n```assembly\ncrp reg(ax), reg(?)     0010 00 01  21\ncrp reg(bx), reg(?)     0010 01 01  25\ncrp reg(cx), reg(?)     0010 10 01  29\ncrp reg(dx), reg(?)     0010 11 01  2D\n\ncrp reg(ax), memory     0010 00 10  22\ncrp reg(bx), memory     0010 01 10  26\ncrp reg(cx), memory     0010 10 10  2A\ncrp reg(dx), memory     0010 11 10  2E\n\ncrp reg(ax), immediate  0010 00 11  23\ncrp reg(bx), immediate  0010 01 11  27\ncrp reg(cx), immediate  0010 10 11  2B\ncrp reg(dx), immediate  0010 11 11  2F\n```\n\n#### CIK\n```assembly\ncik reg(ax), reg(?)     0011 00 01  31\ncik reg(bx), reg(?)     0011 01 01  35\ncik reg(cx), reg(?)     0011 10 01  39\ncik reg(dx), reg(?)     0011 11 01  3D\n\ncik reg(ax), memory     0011 00 10  32\ncik reg(bx), memory     0011 01 10  36\ncik reg(cx), memory     0011 10 10  3A\ncik reg(dx), memory     0011 11 10  3E\n\ncik reg(ax), immediate  0011 00 11  33\ncik reg(bx), immediate  0011 01 11  37\ncik reg(cx), immediate  0011 10 11  3B\ncik reg(dx), immediate  0011 11 11  3F\n```\n\n#### BOL\n```assembly\nbol reg(ax), reg(?)     0011 00 01  41\nbol reg(bx), reg(?)     0011 01 01  45\nbol reg(cx), reg(?)     0011 10 01  49\nbol reg(dx), reg(?)     0011 11 01  4D\n\nbol reg(ax), memory     0011 00 10  42\nbol reg(bx), memory     0011 01 10  46\nbol reg(cx), memory     0011 10 10  4A\nbol reg(dx), memory     0011 11 10  4E\n\nbol reg(ax), immediate  0011 00 11  43\nbol reg(bx), immediate  0011 01 11  47\nbol reg(cx), immediate  0011 10 11  4B\nbol reg(dx), immediate  0011 11 11  4F\n```\n\n#### VE\n```assembly\nve reg(ax), reg(?)      0101 00 01  51\nve reg(bx), reg(?)      0101 01 01  55\nve reg(cx), reg(?)      0101 10 01  59\nve reg(dx), reg(?)      0101 11 01  5D\n\nve reg(ax), memory      0101 00 10  52\nve reg(bx), memory      0101 01 10  56\nve reg(cx), memory      0101 10 10  5A\nve reg(dx), memory      0101 11 10  5E\n\nve reg(ax), immediate   0101 00 11  53\nve reg(bx), immediate   0101 01 11  57\nve reg(cx), immediate   0101 10 11  5B\nve reg(dx), immediate   0101 11 11  5F\n```\n\n#### VEYA\n```assembly\nveya reg(ax), reg(?)    0110 00 01  61\nveya reg(bx), reg(?)    0110 01 01  65\nveya reg(cx), reg(?)    0110 10 01  69\nveya reg(dx), reg(?)    0110 11 01  6D\n\nveya reg(ax), memory    0110 00 10  62\nveya reg(bx), memory    0110 01 10  66\nveya reg(cx), memory    0110 10 10  6A\nveya reg(dx), memory    0110 11 10  6E\n\nveya reg(ax), immediate 0110 00 11  63\nveya reg(bx), immediate 0110 01 11  67\nveya reg(cx), immediate 0110 10 11  6B\nveya reg(dx), immediate 0110 11 11  6F\n```\n\n#### DEG\n```assembly\ndeg reg(?)              0111 00 01  71\n\ndeg memory              0111 00 10  72\n\ndeg immediate           0111 00 11  73\n```\n\n#### SS\n```assembly\nss jumping              1000 00 00  80\n```\n\n#### SSD\n```assembly\nssd jumping             1001 00 00  90\n```\n\n#### SN\n```assembly\nsn jumping              1010 00 00  A0\n```\n\n#### SP\n```assembly\nsp jumping              1011 00 00  B0\n```\n\n\n\n\n\n\n\n\n\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcsgn%2Fassembler","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcsgn%2Fassembler","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcsgn%2Fassembler/lists"}