{"id":48486376,"url":"https://github.com/csp02/rv32i","last_synced_at":"2026-04-07T10:01:29.256Z","repository":{"id":346082004,"uuid":"1161779334","full_name":"CSP02/RV32I","owner":"CSP02","description":null,"archived":false,"fork":false,"pushed_at":"2026-03-27T02:35:31.000Z","size":106,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-03-27T15:08:50.565Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/CSP02.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2026-02-19T14:06:46.000Z","updated_at":"2026-03-27T02:35:34.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/CSP02/RV32I","commit_stats":null,"previous_names":["csp02/risc-v-based-on-processor","csp02/rv32i"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/CSP02/RV32I","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CSP02%2FRV32I","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CSP02%2FRV32I/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CSP02%2FRV32I/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CSP02%2FRV32I/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/CSP02","download_url":"https://codeload.github.com/CSP02/RV32I/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CSP02%2FRV32I/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31508282,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-07T03:10:19.677Z","status":"ssl_error","status_checked_at":"2026-04-07T03:10:13.982Z","response_time":105,"last_error":"SSL_connect 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and includes core components such as ALU, register file, control unit, and memory modules.\n\n---\n\n## 🏗️ Architecture\n\nThe processor is divided into the following pipeline stages:\n\n1. **IF (Instruction Fetch)**  \n2. **ID (Instruction Decode)**  \n3. **EX (Execute)**  \n4. **MEM (Memory Access)**  \n5. **WB (Write Back)**  \n\nPipeline registers are used between each stage to ensure proper data flow.\n\n---\n\n## ⚙️ Features\n\n- 5-stage pipelined architecture  \n- Instruction execution using RV32I base subset  \n- Modular RTL design (ALU, Control Unit, Register File, Memory)  \n- Simulation-based verification  \n- Clean separation of datapath and control logic  \n\n---\n\n## 🔍 Current Status\n\n✅ Base pipeline implementation completed  \n✅ Instruction execution verified through simulation  \n🚧 Hazard handling (data/control hazards) – In Progress  \n🚧 Branch prediction – Planned  \n\n---\n\n## 🧪 Simulation \u0026 Results\n\n- Functional verification performed using testbenches  \n- Instruction flow validated across pipeline stages  \n- Waveforms confirm correct execution of instructions  \n\n\n---\n\n## 🧱 Modules\n\n- ALU  \n- Register File  \n- Control Unit  \n- Instruction Memory  \n- Data Memory  \n- Pipeline Registers  \n\n---\n\n## 📌 Applications\n\n- Understanding pipelined processor design  \n- Instruction-level parallelism concepts  \n- Foundation for advanced CPU design (hazards, forwarding, branch prediction)  \n\n---\n\n## 🚀 Future Work\n\n- Implement hazard detection and forwarding unit  \n- Add branch prediction mechanism  \n- Extend instruction support  \n- Optimize pipeline performance  \n\n---\n\n## 🛠️ Tools Used\n\n- Verilog HDL  \n- Xilinx Vivado  \n- Simulation Testbenches  \n\n---\n\n## 📂 Repository Structure\n/source -\u003e RTL design files\n/testbench -\u003e Simulation testbenches\n/docs -\u003e Diagrams and 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