{"id":19092191,"url":"https://github.com/cvut/qtmips","last_synced_at":"2025-04-09T08:08:49.178Z","repository":{"id":43360428,"uuid":"171281293","full_name":"cvut/QtMips","owner":"cvut","description":"MIPS CPU emulator","archived":false,"fork":false,"pushed_at":"2025-03-24T23:41:54.000Z","size":2749,"stargazers_count":61,"open_issues_count":0,"forks_count":13,"subscribers_count":9,"default_branch":"master","last_synced_at":"2025-04-02T02:22:47.610Z","etag":null,"topics":["emulator","mips"],"latest_commit_sha":null,"homepage":"https://github.com/cvut/QtMips","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cvut.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-02-18T12:35:36.000Z","updated_at":"2025-04-01T04:02:20.000Z","dependencies_parsed_at":"2025-01-17T12:12:30.723Z","dependency_job_id":"cdd6bfb8-e480-467c-aaf1-61fef7f517e7","html_url":"https://github.com/cvut/QtMips","commit_stats":{"total_commits":679,"total_committers":11,"mean_commits":61.72727272727273,"dds":"0.48453608247422686","last_synced_commit":"0c7291df1bc58cf6e062a757c085a66710e90c3e"},"previous_names":[],"tags_count":12,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2FQtMips","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2FQtMips/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2FQtMips/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2FQtMips/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cvut","download_url":"https://codeload.github.com/cvut/QtMips/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247999860,"owners_count":21031046,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["emulator","mips"],"created_at":"2024-11-09T03:18:30.054Z","updated_at":"2025-04-09T08:08:49.158Z","avatar_url":"https://github.com/cvut.png","language":"C++","readme":"# QtMips\n\n[![OpenHub](https://www.openhub.net/p/QtMips/widgets/project_thin_badge?format=gif)](https://www.openhub.net/p/QtMips) [![build status](https://dev.azure.com/qtmips/qtmips/_apis/build/status/cvut.QtMips?branchName=master)](https://dev.azure.com/qtmips/QtMips/_build/latest?definitionId=1\u0026branchName=master)\n\nMIPS CPU simulator for education purposes with pipeline and cache visualizations.\n\nDeveloped by the [Computer Architectures Education](http://comparch.edu.cvut.cz) project\nat [Czech Technical University](http://www.cvut.cz/).\n\nImplemented to support following courses in the past (switched to RISC-V now):\n\n- [B35APO - Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo)\n- [B4M35PAP - Advanced Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b4m35pap/start)\n\nat [Faculty of Electrical Engineering](http://www.fel.cvut.cz) [Czech Technical University](http://www.cvut.cz/)\n\n## Ongoing Development\n\n* QtRVSim - [RISC-V](https://riscv.org/) architecture based edition ([https://github.com/cvut/qtrvsim](https://github.com/cvut/qtrvsim)), suggested for future contributions\n* Space for QtMips examples and students' contributions [https://github.com/cvut/QtMips-Playground](https://github.com/cvut/QtMips-Playground)\n\n## Documentation\n\nThe project has started as diploma theses work of Karel Kočí. The complete text of the thesis [Graphical CPU Simulator with Cache Visualization](https://dspace.cvut.cz/bitstream/handle/10467/76764/F3-DP-2018-Koci-Karel-diploma.pdf)\nis available from the online archive of the [Czech Technical University in Prague](https://www.cvut.cz/). The document provides analysis of available alternative simulators, overview of the project architecture and basic usage information.\n\nThe used [MIPS CPU](https://en.wikipedia.org/wiki/MIPS_architecture) building block diagram,\nand a pipeline model matches lecture slides prepared by Michal Štepanovský for the subject\n[Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo/start).\nThe course is based on the book  [Computer Organization and Design, The HW/SW Interface](https://www.elsevier.com/books/computer-organization-and-design-mips-edition/patterson/978-0-12-407726-3) written by\nprofessors Patterson and Hennessy.\n\nAdditional documentation can be found in subdirectory [`docs`](docs)\nof the project.\n\n## Try it out! (WebAssembly)\n\nQtMips is experimentally available for [WebAssembly](https://webassembly.org/)\nand it can be run in most browsers without installation.\n\n**[QtMips online](https://comparch.edu.cvut.cz/qtmips/app)**\n\nWebAssembly version is experimental and has some usability limitations compared\nto the native application.\n\n## Build and packages\n\n### Build Dependencies\n\n- Qt 5 or 6\n- elfutils (optional; libelf works too but there can be some problems)\n\n### General Compilation\n\n```shell\ncmake -DCMAKE_BUILD_TYPE=Release /path/to/qtmips\nmake\n```\n\nWhere `/path/to/qtmips` is path to this project root. The built binaries are to be found in the directory `target`\nin the build directory (the one, where cmake was called).\n\n### Building from source on macOS\n\nInstall the latest version of **Xcode** from the App Store. Then open a terminal and execute xcode-select --install to\ninstall Command Line Tools. Then open Xcode, accept the license agreement and wait for it to install any additional\ncomponents. After you finally see the \"Welcome to Xcode\" screen, from the top bar choose Xcode -\u003e Preferences -\u003e\nLocations -\u003e Command Line Tools and select an SDK version.\n\nInstall [Homebrew](https://brew.sh/) and use it to install Qt and libelf. (__Installing libelf is optional. If libelf is\nnot found in the system, local fallback is used.__)\n\n```shell\nbrew install qt libelf\n```\n\nThen build as in general compilation (above).\n\n### Download Binary Packages\n\n* [https://github.com/cvut/QtMips/releases](https://github.com/cvut/QtMips/releases) - archives with Windows and generic GNU/Linux binaries\n* [https://launchpad.net/~ppisa/+archive/ubuntu/qtmips](https://launchpad.net/~ppisa/+archive/ubuntu/qtmips) - Ubuntu packages for Disco, Cosmic, Bionic and Xenial releases.\n* [https://build.opensuse.org/repositories/home:ppisa/qtmips](https://build.opensuse.org/repositories/home:ppisa/qtmips) - Open Build Service build for Fedora_29, Fedora_Rawhide, Raspbian_9.0, SLE_15, openSUSE_Leap_15.0_Ports, openSUSE_Leap_15.0, openSUSE_Leap_15.1, openSUSE_Leap_42.3, openSUSE_Leap_42.3_Ports, openSUSE_Tumbleweed and Debian\n* [https://software.opensuse.org//download.html?project=home%3Appisa\u0026package=qtmips](https://software.opensuse.org//download.html?project=home%3Appisa\u0026package=qtmips) - Open Build Service binary packages\n\n## Accepted Binary Formats\n\nThe simulator accepts ELF statically linked executables compiled for 32-bit big-endian and little-endian MISP targets.\n\nOptimal is use of plain mips-elf GCC toolchain.\n\nFor more refer to the [supported executable formats](docs/exec-formats-and-tools.md)\ndocumentation in the [`docs`](docs) projects subdirectory.\n\n## Integrated Assembler\n\nBasic integrated assembler is included in the simulator. It recognizes basic MIPS instructions and `la` and `li` pseudo\ninstructions. Small subset of\n[GNU assembler](https://sourceware.org/binutils/docs/as/) directives is recognized as well.\nNext directives are\nrecognized: `.word`, `.orig`, `.set`/`.equ`, `.ascii` and `.asciz`.\nSome other directives are simply ignored: `.data`, `.text`, `.globl`, `.end` and `.ent`.\nThis allows to write code which can be compiled by both - integrated and full-featured\nassembler. Addresses are assigned\nto labels/symbols which are stored in symbol table. Addition, subtraction, multiplication, divide and bitwise and and\nor are recognized.\n\n## Support to call external make utility\n\nThe action \"Build executable by external make\" call \"make\" program. If the action is invoked and some of source editors\nselected in main windows tabs then the \"make\" is started in the corresponding directory. Else directory of last selected\neditor is chosen. If no editor is open then directory of last loaded ELF executable are used as \"make\" start path. If\neven that is not an option then default directory when the emulator has been started is used.\n\n## Tests\n\nTests are managed by CTest (part of CMake). To build and run all tests, use this commands:\n\n```bash\ncmake -DCMAKE_BUILD_TYPE=Release /path/to/qtmips\nmake\nctest\n```\n\n## Peripherals\n\nThe simulator implements emulation of two peripherals for now. Base addresses are selected such way that they are\naccessible by 16 immediate offset which uses register 0 (`zero`) as base.\n\nThe first is simple serial port (UART). It support transmission\n(Tx) and reception (Rx). Receiver status register (`SERP_RX_ST_REG`)\nimplements two bits. Read-only bit 0 (`SERP_RX_ST_REG_READY`)\nis set to one if there is unread character available in the receiver data register (`SERP_RX_DATA_REG`). The bit 1\n(`SERP_RX_ST_REG_IE`) can be written to 1 to enable interrupt request when unread character is available. The\ntransmitter status register (`SERP_TX_ST_REG`) bit 0\n(SERP_TX_ST_REG_READY) signals by value 1 that UART is ready and can accept next character to be sent. The bit 1\n(`SERP_TX_ST_REG_IE`) enables generation of interrupt. The register `SERP_TX_DATA_REG` is actual Tx buffer. The LSB byte\nof written word is transmitted to the terminal window. Definition of peripheral base address and registers\noffsets (`_o`) and individual fields masks (`_m`) follows\n\n```\n#define SERIAL_PORT_BASE   0xffffc000\n\n#define SERP_RX_ST_REG_o           0x00\n#define SERP_RX_ST_REG_READY_m      0x1\n#define SERP_RX_ST_REG_IE_m         0x2\n\n#define SERP_RX_DATA_REG_o         0x04\n\n#define SERP_TX_ST_REG_o           0x08\n#define SERP_TX_ST_REG_READY_m      0x1\n#define SERP_TX_ST_REG_IE_m         0x2\n\n#define SERP_TX_DATA_REG_o         0x0c\n```\n\nThe UART registers region is mirrored on the address 0xffff0000 to enable use of programs initially written\nfor [SPIM](http://spimsimulator.sourceforge.net/)\nor [MARS](http://courses.missouristate.edu/KenVollmar/MARS/) emulators.\n\nThe another peripheral allows to set three byte values concatenated to single word (read-only KNOBS_8BIT register)\nfrom user panel set by knobs and display one word in hexadecimal, decimal and binary format (`LED_LINE` register). There\nare two other words writable which control color of RGB LED 1 and 2\n(registers `LED_RGB1` and `LED_RGB2`).\n\n```\n#define SPILED_REG_BASE    0xffffc100\n\n#define SPILED_REG_LED_LINE_o           0x004\n#define SPILED_REG_LED_RGB1_o           0x010\n#define SPILED_REG_LED_RGB2_o           0x014\n#define SPILED_REG_LED_KBDWR_DIRECT_o   0x018\n\n#define SPILED_REG_KBDRD_KNOBS_DIRECT_o 0x020\n#define SPILED_REG_KNOBS_8BIT_o         0x024\n```\n\nThe simple 16-bit per pixel (RGB565) framebuffer and LCD display are implemented. The framebuffer is mapped into range\nstarting at `LCD_FB_START`\naddress. The display size is 480 x 320 pixel. Pixel format RGB565 expect red component in bits 11 .. 15, green component\nin bits 5 .. 10 and blue component in bits 0 .. 4.\n\n```\n#define LCD_FB_START       0xffe00000\n#define LCD_FB_END         0xffe4afff\n```\n\nLimitation: actual concept of memory view updates and access does not allows to reliably read peripheral registers and\nI/O memory content. It is possible to write into framebuffer memory when cached (from CPU perspective) access to memory\nis selected.\n\n## Interrupts and Coprocessor 0 Support\n\nList of interrupt sources:\n\n| Irq number | Cause/Status Bit | Source                                       |\n|-----------:|-----------------:|:---------------------------------------------|\n| 2 / HW0    | 10               | Serial port ready to accept character to Tx  |\n| 3 / HW1    | 11               | There is received character ready to be read |\n| 7 / HW5    | 15               | Counter reached value in Compare register    |\n\nFollowing coprocessor 0 registers are recognized\n\n| Number | Name       | Description |\n|-------:|:-----------|:------------|\n|  $4,2  | UserLocal  | Used as TLS base by operating system usually |\n|  $8,0  | BadVAddr   | Reports the address for the most recent address-related exception |\n|  $9,0  | Count      | Processor cycle count |\n| $11,0  | Compare    | Timer interrupt control |\n| $12,0  | Status     | Processor status and control |\n| $13,0  | Cause      | Cause of last exception |\n| $14,0  | EPC        | Program counter at last exception |\n| $15,1  | EBase      | Exception vector base register |\n| $16,0  | Config     | Configuration registers |\n\n`mtc0` and `mfc0` are used to copy value from/to general puropose registers to/from comprocessor 0 register.\n\nHardware/special registers implemented:\n\n| Number | Name       | Description |\n|-------:|:-----------|:------------|\n|  0     | CPUNum     | CPU number, fixed to 0  |\n|  1     | SYNCI_Step | Increment required for instruction cache synchronization |\n|  2     | CC         | Cycle counter |\n|  3     | CCRes      | Cycle counter resolution, fixed on 1 |\n| 29     | UserLocal  | Read only value of Coprocessor 0 $4,2 register |\n\nSequence to enable serial port receive interrupt:\n\nDecide location of interrupt service routine the first. The default address is 0x80000180. The base can be\nchanged (`EBase` register) and then PC is set to address EBase + 0x180. This is in accordance with MIPS release 1 and 2\nmanuals.\n\nEnable bit 11 (interrupt mask) in the Status register. Ensure that bit 1 (`EXL`)\nis zero and bit 0 (`IE`) is set to one.\n\nEnable interrupt in the receiver status register (bit 1 of `SERP_RX_ST_REG`).\n\nWrite character to the terminal. It should be immediately consumed by the serial port receiver if interrupt is enabled\nin `SERP_RX_ST_REG`. CPU should report interrupt exception and when it propagates to the execution phase `PC` is set to\nthe interrupt routine start address.\n\nSome hints how to direct linker to place interrupt handler routine at appropriate address. Implement interrupt routine\nin new section\n\n```\n.section .irq_handler, \"ax\"\n```\n\nUse next linker option to place section start at right address\n\n```\n -Wl,--section-start=.irq_handler=0x80000180\n```\n\n## System Calls Support\n\nThe emulator includes support for a few Linux kernel systemcalls. The MIPS O32 ABI is used.\n\n| Register                           | use on input          | use on output                     | Note\n|:-----------------------------------|:----------------------|:----------------------------------|:-------\n| $at ($1)                           | —                     | (caller saved)                    |\n| $v0 ($2)                           | syscall number        | return value                      |\n| $v1 ($3)                           | —                     | 2nd fd only for pipe(2)           |\n| $a0 ... $a2 ($4 ... $6)            | syscall arguments     | returned unmodified               |\n| $a3 ($7)                           | 4th syscall argument  | $a3 set to 0/1 for success/error  |\n| $t0 ... $t9 ($8 ... $15, $24, $25) | —                     | (caller saved)                    |\n| $s0 ... $s7 ($16 ... $23)          | —                     | (callee saved)                    |\n| $k0, $k1 ($26, $27)                |                       |                                   |\n| $gp ($28)                          |                       | (callee saved)                    |\n| $sp ($29)                          |                       | (callee saved)                    |\n| $fp or $s8 ($30)                   |                       | (callee saved)                    |\n| $ra ($31)                          |                       | (callee saved)                    |\n| $hi, $lo                           | —                     | (caller saved)                    |\n\nThe first four input arguments are passed in registers $a0 to $a3, if more arguments are required then fifth and\nfollowing arguments are stored on the stack.\n\nSupported syscalls:\n\n#### void [exit](http://man7.org/linux/man-pages/man2/exit.2.html)(int status) __NR_exit (4001)\n\nStop/end execution of the program. The argument is exit status code, zero means OK, other values informs about error.\n\n#### ssize_t [read](http://man7.org/linux/man-pages/man2/read.2.html)(int fd, void *buf, size_t count) __NR_read (4003)\n\nRead `count` bytes from open file descriptor `fd`. The emulator maps file descriptors 0, 1 and 2 to the internal\nterminal/console emulator. They can be used without `open` call. If there are no more characters to read from the\nconsole, newline is appended. At most the count bytes read are stored to the memory location specified by `buf`\nargument. Actual number of read bytes is returned.\n\n#### ssize_t [write](http://man7.org/linux/man-pages/man2/write.2.html)(int fd, const void *buf, size_t count) __NR_write (4004)\n\nWrite `count` bytes from memory location `buf` to the open file descriptor\n`fd`. The same about console for file handles 0, 1 and 2 is valid as for `read`.\n\n#### int [close](http://man7.org/linux/man-pages/man2/close.2.html)(int fd) __NR_close (4006)\n\nClose file associated to descriptor `fd` and release descriptor.\n\n#### int [open](http://man7.org/linux/man-pages/man2/open.2.html)(const char *pathname, int flags, mode_t mode) __NR_open (4005)\n\nOpen file and associate it with the first unused file descriptor number and return that number. If the\noption `OS Emulation`-\u003e`Filesystem root`\nis not empty then the file path `pathname` received from emulated environment is appended to the path specified\nby `Filesystem root`. The host filesystem is protected against attempt to traverse to random directory by use of `..`\npath elements. If the root is not specified then all open files are targetted to the emulated terminal.\n\n#### void * [brk](http://man7.org/linux/man-pages/man2/brk.2.html)(void *addr) __NR_brk (4045)\n\nSet end of the area used by standard heap after end of the program data/bss. The syscall is emulated by dummy\nimplementation. Whole address space up to 0xffff0000 is backuped by automatically attached RAM.\n\n#### int [ftruncate](http://man7.org/linux/man-pages/man2/ftruncate.2.html)(int fd, off_t length) __NR_truncate (4092)\n\nSet length of the open file specified by `fd` to the new `length`. The `length`\nargument is 64-bit even on 32-bit system and for big-endian MIPS it is apssed as higher part and the lower part in the\nsecond and third argument.\n\n#### ssize_t [readv](http://man7.org/linux/man-pages/man2/readv.2.html)(int fd, const struct iovec *iov, int iovcnt) __NR_Linux (4145)\n\nThe variant of `read` system call where data to read are would be stored to locations specified by `iovcnt` pairs of\nbase address, length pairs stored in memory at address pass in `iov`.\n\n#### ssize_t [writev](http://man7.org/linux/man-pages/man2/writev.2.html)(int fd, const struct iovec *iov, int iovcnt) __NR_Linux (4146)\n\nThe variant of `write` system call where data to write are defined by `iovcnt`\npairs of base address, length pairs stored in memory at address pass in `iov`.\n\n#### int [set_thread_area](http://man7.org/linux/man-pages/man2/set_thread_area.2.html)(unsigned long addr) __NR_set_thread_area (4283)\n\nSet TLS base into `C0` `user_local` register accessible by `rdhwr` instruction..\n\n## Special instructions support\n\n#### RDHWR - read hardware registers\nSupported registers described in Interrupts and Coprocessor 0 Support section\n\n#### SYNC - memory barrier between preceding and following reads/writes\nIt is implemented as NOP because memory access is processed in order and only in the memory stage.\n\n#### SYNCI - synchronize/propagate modification to the instruction cache memory and pipeline\nThe function codes for different modes nor address/cache line which should be synchronized\nis recognized. Instruction is\nimplemented as full instruction and data cache flush.\n\n#### CACHE - cache maintenance operations\nFunction is not decoded, full flush of data and instruction caches is performed.\n\n### Limitations of the Implementation\n* Only very minimal support for privileged instruction is implemented for now.\n  Only RDHWR, SYNCI, CACHE and some coprocessor 0 registers implemented. TLB and virtual\n  memory and complete exception model are not implemented.\n* Coprocessors (so no floating point unit and only limited coprocessor 0)\n* Memory access stall (stalling execution because of cache miss would be pretty annoying for users so difference between\n  cache and memory is just in collected statistics)\n* Only limited support for interrupts and exceptions. When `syscall` or `break`\n  instruction is recognized, emulation stops. Single step proceed after instruction.\n\n## List of Actually Supported Instructions\n\nADD ADDI ADDIU ADDU AND ANDI BEQ BEQL BGEZ BGEZAL BGEZALL BGEZL BGTZ BGTZL BLEZ BLEZL BLTZ BLTZAL BLTZALL BLTZL BNE BNEL\nBREAK CACHE CLO CLZ DIV DIVU ERET EXT INS J JAL JALR JR LB LBU LH LHU LL LUI LW LWC1 LWD1 LWL LWR MADD MADDU MFC0 MFHI MFLO MFMC0 MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MUL MULT MULTU NOR OR ORI PREF RDHWR ROTR ROTRV SB SC SDC1 SEB SEH SH SLL\nSLLV SLT SLTI SLTIU SLTU SRA SRAV SRL SRLV SUB SUBU SW SWC1 SWL SWR SYNC SYNCI SYSCALL TEQ TEQI TGE TGEI TGEIU TGEU TLT\nTLTI TLTIU TLTU TNE TNEI WSBH XOR XORI \n\n## Links to Resources and Similar Projects\n\n* SPIM/QtSPIM: A MIPS32 Simulator [http://spimsimulator.sourceforge.net/](http://spimsimulator.sourceforge.net/)\n* MARS: IDE with detailed help and hints [http://courses.missouristate.edu/KenVollmar/MARS/index.htm](http://courses.missouristate.edu/KenVollmar/MARS/index.htm)\n* EduMIPS64: 1x fixed and 3x FP pipelines [https://www.edumips.org/](https://www.edumips.org/)\n* Jakub Dupak: [Graphical RISC-V Architecture Simulator - Memory Model and Project Management](https://dspace.cvut.cz/bitstream/handle/10467/94446/F3-BP-2021-Dupak-Jakub-thesis.pdf) documents QtMips and qtmips development\n\n## Copyright\n\n- Copyright (c) 2017-2019 Karel Koci \u003ccynerd@email.cz\u003e\n- Copyright (c) 2019-2021 Pavel Pisa \u003cpisa@cmp.felk.cvut.cz\u003e\n- Copyright (c) 2020-2021 Jakub Dupak \u003cdev@jakubdupak.com\u003e\n\n## License\n\nThis project is licensed under `GPL-3.0-or-later`. The full text of the license is in the [LICENSE](LICENSE) file. \nThe license applies to all files except for directories named `external` and files in them. Files in external \ndirectories have a separate license compatible with the projects license.\n\nThis program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public \nLicense as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later \nversion.\n\nThis program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied \nwarranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License along with this program. \nIf not, see [https://www.gnu.org/licenses/](https://www.gnu.org/licenses/).\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcvut%2Fqtmips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcvut%2Fqtmips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcvut%2Fqtmips/lists"}