{"id":19092193,"url":"https://github.com/cvut/qtrvsim","last_synced_at":"2025-05-15T10:06:58.534Z","repository":{"id":40559885,"uuid":"318563203","full_name":"cvut/qtrvsim","owner":"cvut","description":"RISC-V CPU simulator for education purposes","archived":false,"fork":false,"pushed_at":"2025-05-02T19:21:21.000Z","size":3921,"stargazers_count":549,"open_issues_count":27,"forks_count":73,"subscribers_count":15,"default_branch":"master","last_synced_at":"2025-05-02T20:20:23.737Z","etag":null,"topics":["computer-architecture","cpu-emulator","risc-v","teaching"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cvut.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2020-12-04T15:51:43.000Z","updated_at":"2025-05-02T19:07:36.000Z","dependencies_parsed_at":"2023-02-16T23:46:21.576Z","dependency_job_id":"938f8ac6-fba9-47cb-accb-1b3c9b21d4ed","html_url":"https://github.com/cvut/qtrvsim","commit_stats":null,"previous_names":[],"tags_count":20,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2Fqtrvsim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2Fqtrvsim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2Fqtrvsim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cvut%2Fqtrvsim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cvut","download_url":"https://codeload.github.com/cvut/qtrvsim/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254319720,"owners_count":22051073,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["computer-architecture","cpu-emulator","risc-v","teaching"],"created_at":"2024-11-09T03:18:30.100Z","updated_at":"2025-05-15T10:06:53.518Z","avatar_url":"https://github.com/cvut.png","language":"C++","funding_links":[],"categories":["C++"],"sub_categories":[],"readme":"# QtRvSim–RISC-V CPU simulator for education\n\n![QtRvSim screenshot](data/screenshots/intro.webp)\n\nDeveloped by the [Computer Architectures Education](http://comparch.edu.cvut.cz) project\nat [Czech Technical University](http://www.cvut.cz/).\n\n**Are you using QtRvSim at your organization?** [Please, let us know in the discussion!](https://github.com/cvut/qtrvsim/discussions/136)\n\n## Table of contents\n\n\u003c!-- TOC start --\u003e\n\n- [Try it out! (WebAssembly)](#try-it-out-webassembly)\n- [Build and packages](#build-and-packages)\n  - [Build Dependencies](#build-dependencies)\n  - [General Compilation](#general-compilation)\n  - [Building from source on macOS](#building-from-source-on-macos)\n  - [Download Binary Packages](#download-binary-packages)\n  - [Nix package](#nix-package)\n  - [Tests](#tests)\n- [Documentation](#documentation)\n- [Accepted Binary Formats](#accepted-binary-formats)\n  - [LLVM toolchain usage](#llvm-toolchain-usage)\n  - [GNU toolchain usage](#gnu-toolchain-usage)\n  - [GNU 64-bit toolchain use for RV32I target](#gnu-64-bit-toolchain-use-for-rv32i-target)\n- [Integrated Assembler](#integrated-assembler)\n- [Support to call external make utility](#support-to-call-external-make-utility)\n- [Advanced functionalities](#advanced-functionalities)\n  - [Peripherals](#peripherals)\n  - [Interrupts and Control and Status Registers](#interrupts-and-control-and-status-registers)\n  - [System Calls Support](#system-calls-support)\n- [Limitations of the Implementation](#limitations-of-the-implementation)\n  - [QtRvSim limitations](#qtrvsim-limitations)\n  - [List of Currently Supported Instructions](#list-of-currently-supported-instructions)\n- [Links to Resources and Similar Projects](#links-to-resources-and-similar-projects)\n- [Copyright](#copyright)\n- [License](#license)\n\n\u003c!-- TOC end --\u003e\n\n## Try it out! (WebAssembly)\n\nQtRVSim is experimentally available for [WebAssembly](https://webassembly.org/) and it can be run in most browsers\nwithout installation. **[QtRVSim online](https://comparch.edu.cvut.cz/qtrvsim/app)**\n\n**Note, that WebAssembly version is experimental.**\nPlease, report any difficulties via [GitHub issues](https://github.com/cvut/qtrvsim/issues/new).\n\n## Build and packages\n\n[![Packaging status](https://repology.org/badge/vertical-allrepos/qtrvsim.svg)](https://repology.org/project/qtrvsim/versions)\n\n[![build result](https://build.opensuse.org/projects/home:jdupak/packages/qtrvsim/badge.svg?type=default)](https://build.opensuse.org/package/show/home:jdupak/qtrvsim)\n\n### Build Dependencies\n\n- Qt 5 (minimal tested version is 5.9.5), experimental support of Qt 6\n- elfutils (optional; libelf works too but there can be some problems)\n\n### Quick Compilation on Linux\n\nOn Linux, you can use a wrapper Makefile and run `make` in the project root directory. It will create a build directory\nand run CMake in it. Available targets are: `release` (default) and `debug`.\n\nNote for packagers: This Makefile is deleted by CMake when source archive is created to avoid any ambiguity. Packages\nshould invoke CMake directly.\n\n### General Compilation\n\n```shell\ncmake -DCMAKE_BUILD_TYPE=Release /path/to/qtrvsim\nmake\n```\n\nWhere `/path/to/qtrvsim` is path to this project root. The built binaries are to be found in the directory `target`in\nthe build directory (the one, where cmake was called).\n\n`-DCMAKE_BUILD_TYPE=Debug` builds development version including sanitizers.\n\nIf no build type is supplied, `Debug` is the default.\n\n### Building from source on macOS\n\nInstall the latest version of **Xcode** from the App Store. Then open a terminal and execute `xcode-select --install` to\ninstall Command Line Tools. Then open Xcode, accept the license agreement and wait for it to install any additional\ncomponents. After you finally see the \"Welcome to Xcode\" screen, from the top bar\nchoose `Xcode -\u003e Preferences -\u003e Locations -\u003e Command Line Tools` and select an SDK version.\n\nInstall [Homebrew](https://brew.sh/) and use it to install Qt. (macOS builds must use the bundled libelf)\n\n```shell\nbrew install qt\n```\n\nNow build the project the same way as in general compilation ([above](#general-compilation)).\n\n### Download Binary Packages\n\n- [https://github.com/cvut/qtrvsim/releases](https://github.com/cvut/qtrvsim/releases)\n    - archives with Windows and generic GNU/Linux binaries\n- [https://build.opensuse.org/repositories/home:jdupak/qtrvsim](https://build.opensuse.org/repositories/home:jdupak/qtrvsim)\n- [https://software.opensuse.org/download.html?project=home%3Ajdupak\u0026package=qtrvsim](https://software.opensuse.org/download.html?project=home%3Ajdupak\u0026package=qtrvsim)\n    - Open Build Service binary packages\n- [https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa](https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa)\n    - Ubuntu PPA archive\n\n```bash\nsudo add-apt-repository ppa:qtrvsimteam/ppa\nsudo apt-get update\nsudo apt-get install qtrvsim\n```\n\n### Nix package\n\nQtRVSim provides a Nix package as a part of the repository. You can build and install it by a command bellow. Updates\nhave to be done manually by checking out the git. NIXPKGS package is in PR phase.\n\n```shell\nnix-env -if .\n```\n\n### Tests\n\nTests are managed by CTest (part of CMake). To build and run all tests, use this commands:\n\n```bash\ncmake -DCMAKE_BUILD_TYPE=Release /path/to/QtRVSim\nmake\nctest\n```\n\n## Documentation\n\nMain documentation is provided in this README and in subdirectories [`docs/user`](docs/user)\nand [`docs/developer`](docs/developer).\n\nThe project was developed and extended as theses of Karel Kočí, Jakub Dupak and Max Hollmann. See section [Resources and Publications](#resources-and-publications) for links and references.\n\n## Accepted Binary Formats\n\nThe simulator accepts ELF statically linked executables compiled for RISC-V target (`--march=rv64g`).\nThe simulator will automatically select endianness based on the ELF file header.\nSimulation will execute as XLEN=32 or XLEN=32 according to the ELF file header.\n\n- 64-bit RISC-V ISA RV64IM and 32-bit RV32IM ELF executables are supported.\n- Compressed instructions are not yet supported.\n\nYou can use compile the code for simulation using specialized RISC-V GCC/Binutils toolchain (`riscv32-elf`) or using\nunified Clang/LLVM toolchain with [LLD](https://lld.llvm.org/). If you have Clang installed, you don't need any\nadditional tools. Clang can be used on Linux, Windows, macOS and others...\n\n### LLVM toolchain usage\n\n```shell\nclang --target=riscv32 -march=rv32g -nostdlib -static -fuse-ld=lld test.S -o test\nllvm-objdump -S test\n```\n\n### GNU toolchain usage\n\n```shell\nriscv32-elf-as test.S -o test.o\nriscv32-elf-ld test.o -o test\nriscv32-elf-objdump -S test\n```\n\nor\n\n```shell\nriscv32-elf-gcc test.S -o test\nriscv32-elf-objdump -S test\n```\n\n### GNU 64-bit toolchain use for RV32I target\n\nMultilib supporting 64-bit embedded toolchain can be used for to build executable\n\n```shell\nriscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -nostdlib -o test test.c crt0local.S -lgcc\n```\n\nThe global pointer and stack has to be set to setup runtime C code conformant environment. When no other C library is\nused then next simple `crt0local.S` can be used.\n\n\u003cdetails\u003e\n  \u003csummary\u003eexample code\u003c/summary\u003e\n\n```asm\n/* minimal replacement of crt0.o which is else provided by C library */\n\n.globl main\n.globl _start\n.globl __start\n\n.option norelax\n\n.text\n\n__start:\n_start:\n        .option push\n        .option norelax\n        la gp, __global_pointer$\n        .option pop\n        la      sp, __stack_end\n        addi    a0, zero, 0\n        addi    a1, zero, 0\n        jal     main\nquit:\n        addi    a0, zero, 0\n        addi    a7, zero, 93  /* SYS_exit */\n        ecall\n\nloop:   ebreak\n        beq     zero, zero, loop\n\n.bss\n\n__stack_start:\n        .skip   4096\n__stack_end:\n\n.end _start\n```\n\n\u003c/details\u003e\n\n## Integrated Assembler\n\nBasic integrated assembler is included in the simulator. Small subset of\n[GNU assembler](https://sourceware.org/binutils/docs/as/) directives is recognized as well. Next directives are\nrecognized: `.word`, `.orig`, `.set`\n/`.equ`, `.ascii` and `.asciz`. Some other directives are simply ignored: `.data`, `.text`, `.globl`, `.end` and `.ent`.\nThis allows to write code which can be compiled by both - integrated and full-featured assembler. Addresses are assigned\nto labels/symbols which are stored in symbol table. Addition, subtraction, multiplication, divide and bitwise and or are\nrecognized.\n\n## Support to call external make utility\n\nThe action \"Build executable by external make\" call \"make\" program. If the action is invoked, and some source editors\nselected in main windows tabs then the \"make\" is started in the corresponding directory. Else directory of last selected\neditor is chosen. If no editor is open then directory of last loaded ELF executable are used as \"make\" start path. If\neven that is not an option then default directory when the emulator has been started is used.\n\n## Advanced functionalities\n\n### Peripherals\n\n\u003cdetails\u003e\n  \u003csummary\u003eEmuated LCD, knobs, buttons, serial port, timer...\u003c/summary\u003e\n\nThe simulator implements emulation of two peripherals for now.\n\nThe first is simple serial port (UART). It support transmission\n(Tx) and reception (Rx). Receiver status register (`SERP_RX_ST_REG`)\nimplements two bits. Read-only bit 0 (`SERP_RX_ST_REG_READY`)\nis set to one if there is unread character available in the receiver data register (`SERP_RX_DATA_REG`). The bit 1\n(`SERP_RX_ST_REG_IE`) can be written to 1 to enable interrupt request when unread character is available. The\ntransmitter status register (`SERP_TX_ST_REG`) bit 0\n(SERP_TX_ST_REG_READY) signals by value 1 that UART is ready and can accept next character to be sent. The bit 1\n(`SERP_TX_ST_REG_IE`) enables generation of interrupt. The register `SERP_TX_DATA_REG` is actual Tx buffer. The LSB byte\nof written word is transmitted to the terminal window. Definition of peripheral base address and registers\noffsets (`_o`) and individual fields masks (`_m`) follows\n\n```\n#define SERIAL_PORT_BASE   0xffffc000\n\n#define SERP_RX_ST_REG_o           0x00\n#define SERP_RX_ST_REG_READY_m      0x1\n#define SERP_RX_ST_REG_IE_m         0x2\n\n#define SERP_RX_DATA_REG_o         0x04\n\n#define SERP_TX_ST_REG_o           0x08\n#define SERP_TX_ST_REG_READY_m      0x1\n#define SERP_TX_ST_REG_IE_m         0x2\n\n#define SERP_TX_DATA_REG_o         0x0c\n```\n\nThe UART registers region is mirrored on the address 0xffff0000 to enable use of programs initially written\nfor [SPIM](http://spimsimulator.sourceforge.net/) or [MARS](http://courses.missouristate.edu/KenVollmar/MARS/)\nemulators.\n\nThe another peripheral allows to set three byte values concatenated to single word (read-only `KNOBS_8BIT` register)\nfrom user panel set by knobs and display one word in hexadecimal, decimal and binary format (`LED_LINE` register). There\nare two other words writable which control color of RGB LED 1 and 2\n(registers `LED_RGB1` and `LED_RGB2`).\n\n```\n#define SPILED_REG_BASE    0xffffc100\n\n#define SPILED_REG_LED_LINE_o           0x004\n#define SPILED_REG_LED_RGB1_o           0x010\n#define SPILED_REG_LED_RGB2_o           0x014\n#define SPILED_REG_LED_KBDWR_DIRECT_o   0x018\n\n#define SPILED_REG_KBDRD_KNOBS_DIRECT_o 0x020\n#define SPILED_REG_KNOBS_8BIT_o         0x024\n```\n\nThe simple 16-bit per pixel (RGB565) framebuffer and LCD are implemented. The framebuffer is mapped into range starting\nat `LCD_FB_START` address. The display size is 480 x 320 pixel. Pixel format RGB565 expect red component in bits 11..\n15, green component in bits 5..10 and blue component in bits 0..4.\n\n```\n#define LCD_FB_START       0xffe00000\n#define LCD_FB_END         0xffe4afff\n```\n\nThe basic implementation of RISC-V Advanced Core Local Interruptor\nis implemented with basic support for\n\n- Machine-level Timer Device (MTIMER)\n- Machine-level Software Interrupt Device (MSWI)\n\n```\n#define ACLINT_MSWI        0xfffd0000 // core 0 machine SW interrupt request\n#define ACLINT_MTIMECMP    0xfffd4000 // core 0 compare value\n#define ACLINT_MTIME       0xfffdbff8 // timer base 10 MHz\n#define ACLINT_SSWI        0xfffd0000 // core 0 system SW interrupt request\n```\n\nMore information about ACLINT can be found in [RISC-V Advanced Core Local Interruptor Specification](https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc).\n\n\u003c/details\u003e\n\n### Interrupts and Control and Status Registers\n\n\u003cdetails\u003e\n  \u003csummary\u003eImplemented CSR registers and their usage\u003c/summary\u003e\n\nList of interrupt sources:\n\n| Irq number | mie / mip Bit    | Source                                       |\n|-----------:|-----------------:|:---------------------------------------------|\n| 3          | 3                | Machine software interrupt request           |\n| 7          | 7                | Machine timer interrupt                      |\n| 16         | 16               | There is received character ready to be read |\n| 17         | 17               | Serial port ready to accept character to Tx  |\n\nFollowing Control Status registers are recognized\n\n| Number | Name       | Description                                                         |\n|-------:|:-----------|:--------------------------------------------------------------------|\n|  0x300 | mstatus    | Machine status register. |\n|  0x304 | mie        | Machine interrupt-enable register. |\n|  0x305 | mtvec      | Machine trap-handler base address. |\n|  0x340 | mscratch   | Scratch register for machine trap handlers. |\n|  0x341 | mepc       | Machine exception program counter. |\n|  0x342 | mcause     | Machine trap cause. |\n|  0x343 | mtval      | Machine bad address or instruction. |\n|  0x344 | mip        | Machine interrupt pending. |\n|  0x34A | mtinsr     | Machine trap instruction (transformed). |\n|  0x34B | mtval2     | Machine bad guest physical address. |\n|  0xB00 | mcycle     | Machine cycle counter. |\n|  0xB02 | minstret   | Machine instructions-retired counter. |\n|  0xF11 | mvendorid  | Vendor ID. |\n|  0xF12 | marchid    | Architecture ID. |\n|  0xF13 | mimpid     | Implementation ID. |\n|  0xF14 | mhardid    | Hardware thread ID. |\n\n`csrr`, `csrw`, `csrrs` , `csrrs` and `csrrw` are used to copy and exchange value from/to RISC-V control status registers.\n\nSequence to enable serial port receive interrupt:\n\nDecide location of interrupt service routine the first. The address of the common trap handler is defined by `mtvec` register and then PC is set to this address when exception or interrupt is accepted.\n\nEnable bit 16 in the machine Interrupt-Enable register (`mie`). Ensure that bit 3 (`mstatus.mie` - machine global interrupt-enable) of Machine Status register is set to one.\n\nEnable interrupt in the receiver status register (bit 1 of `SERP_RX_ST_REG`).\n\nWrite character to the terminal. It should be immediately consumed by the serial port receiver if interrupt is enabled\nin `SERP_RX_ST_REG`. CPU should report interrupt exception and when it propagates to the execution phase `PC` is set to\nthe interrupt routine start address.\n\n\u003c/details\u003e\n\n### System Calls Support\n\n\u003cdetails\u003e\n  \u003csummary\u003eSyscall table and documentation\u003c/summary\u003e\n\nThe emulator includes support for a few Linux kernel system calls. The RV32G ilp32 ABI is used.\n\n| Register                           | use on input          | use on output   | Calling Convention             |\n|:-----------------------------------|:----------------------|:----------------|:-------------------------------|\n| zero (x0)                          | —                     | -               | Hard-wired zero                |\n| ra (x1)                            | —                     | (preserved)     | Return address                 |\n| sp (x2)                            | —                     | (callee saved)  | Stack pointer                  |\n| gp (x3)                            | —                     | (preserved)     | Global pointer                  |\n| tp (x4)                            | —                     | (preserved)     | Thread pointer                 |\n| t0 .. t2 (x5 .. x7)                | —                     | -               | Temporaries                    |\n| s0/fp (x8)                         | —                     | (callee saved)  | Saved register/frame pointer   |\n| s1 (x9)                            | —                     | (callee saved)  | Saved register                 |\n| a0 (x10)                           | 1st syscall argument  | return value    | Function argument/return value |\n| a1 (x11)                           | 2nd syscall argument  | -               | Function argument/return value |\n| a2 .. a5 (x12 .. x15)              | syscall arguments     | -               | Function arguments             |\n| a6 (x16)                           | -                     | -               | Function arguments             |\n| a7 (x17)                           | syscall number        | -               | Function arguments             |\n| s2 .. s11 (x18 .. x27)             | —                     | (callee saved)  | Saved registers                |\n| t3 .. t6 (x28 .. x31)              | —                     | -               | Temporaries                    |\n\nThe all system call input arguments are passed in register.\n\nSupported syscalls:\n\n#### void [exit](http://man7.org/linux/man-pages/man2/exit.2.html)(int status) __NR_exit (93)\n\nStop/end execution of the program. The argument is exit status code, zero means OK, other values informs about error.\n\n#### ssize_t [read](http://man7.org/linux/man-pages/man2/read.2.html)(int fd, void *buf, size_t count) __NR_read (63)\n\nRead `count` bytes from open file descriptor `fd`. The emulator maps file descriptors 0, 1 and 2 to the internal\nterminal/console emulator. They can be used without `open` call. If there are no more characters to read from the\nconsole, newline is appended. At most the count bytes read are stored to the memory location specified by `buf`\nargument. Actual number of read bytes is returned.\n\n#### ssize_t [write](http://man7.org/linux/man-pages/man2/write.2.html)(int fd, const void *buf, size_t count) __NR_write (64)\n\nWrite `count` bytes from memory location `buf` to the open file descriptor\n`fd`. The same about console for file handles 0, 1 and 2 is valid as for `read`.\n\n#### int [close](http://man7.org/linux/man-pages/man2/close.2.html)(int fd) __NR_close (57)\n\nClose file associated to descriptor `fd` and release descriptor.\n\n#### int [openat](http://man7.org/linux/man-pages/man2/open.2.html)(int dirfd, const char *pathname, int flags, mode_t mode) __NR_openat (56)\n\nOpen file and associate it with the first unused file descriptor number and return that number. If the\noption `OS Emulation`-\u003e`Filesystem root`\nis not empty then the file path `pathname` received from emulated environment is appended to the path specified\nby `Filesystem root`. The host filesystem is protected against attempt to traverse to random directory by use of `..`\npath elements. If the root is not specified then all open files are targetted to the emulated terminal. Only `TARGET_AT_FDCWD` (`dirfd` = -100) mode is supported.\n\n#### void * [brk](http://man7.org/linux/man-pages/man2/brk.2.html)(void *addr) __NR_brk (214)\n\nSet end of the area used by standard heap after end of the program data/bss. The syscall is emulated by dummy\nimplementation. Whole address space up to 0xffff0000 is backuped by automatically attached RAM.\n\n#### int [ftruncate](http://man7.org/linux/man-pages/man2/ftruncate.2.html)(int fd, off_t length) __NR_truncate (46)\n\nSet length of the open file specified by `fd` to the new `length`. The `length`\nargument is 64-bit even on 32-bit system and it is passed as the lower part and the higher part in the\nsecond and third argument.\n\n#### ssize_t [readv](http://man7.org/linux/man-pages/man2/readv.2.html)(int fd, const struct iovec *iov, int iovcnt) __NR_Linux (65)\n\nThe variant of `read` system call where data to read are would be stored to locations specified by `iovcnt` pairs of\nbase address, length pairs stored in memory at address pass in `iov`.\n\n#### ssize_t [writev](http://man7.org/linux/man-pages/man2/writev.2.html)(int fd, const struct iovec *iov, int iovcnt) __NR_Linux (66)\n\nThe variant of `write` system call where data to write are defined by `iovcnt`\npairs of base address, length pairs stored in memory at address pass in `iov`.\n\n\u003c/details\u003e\n\n## Limitations of the Implementation\n\n- See list of currently supported instructions.\n\n### QtRvSim limitations\n\n* Only very minimal support for privileged instruction is implemented for now (mret).\n* Only machine mode and minimal subset of machine CSRs is implemented.\n* TLB and virtual memory are not implemented.\n* No floating point support\n* Memory access stall (stalling execution because of cache miss would be pretty annoying for users so difference between\n  cache and memory is just in collected statistics)\n* Only limited support for interrupts and exceptions. When `ecall`\n  instruction is recognized, small subset of the Linux kernel system calls\n  can be emulated or simulator can be configured to continue by trap handler\n  on `mtvec` address.\n\n### List of Currently Supported Instructions\n\n- **RV32I**:\n  - **LOAD**: `lw, lh, lb, lwu, lhu, lbu`\n  - **STORE**: `sw, sh, sb, swu, shu, sbu`\n  - **OP**: `add, sub, sll, slt, sltu, xor, srl, sra, or, and`\n  - **MISC-MEM**: `fence, fence.i`\n  - **OP-IMM**: `addi, sll, slti, sltiu, xori, srli, srai, ori, andi, auipc, lui`\n  - **BRANCH**: `beq, bne, btl, bge, bltu, bgtu`\n  - **JUMP**: `jal, jalr`\n  - **SYSTEM**: `ecall, mret, ebreak, csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci`\n- **RV64I**:\n  - **LOAD/STORE**: `lwu, ld, sd`\n  - **OP-32**: `addw, subw, sllw, srlw, sraw, or, and`\n  - **OP-IMM-32**: `addiw, sllw, srliw, sraiw`\n- **Pseudoinstructions**\n  - **BASIC**: `nop`\n  - **LOAD**: `la, li`,\n  - **OP**: `mv, not, neg, negw, sext.b, sext.h, sext.w, zext.b, zext.h, zext.w, seqz, snez, sltz, slgz`\n  - **BRANCH**: `beqz, bnez, blez, bgez, bltz, bgtz, bgt, ble, bgtu, bleu`\n  - **JUMP**: `j, jal, jr, jalr, ret, call, tail`\n- **Extensions**\n  - **RV32M/RV64M**: `mul, mulh, mulhsu, div, divu, rem, remu`\n  - **RV64M**: `mulw, divw, divuw, remw, remuw`\n  - **RV32A/RV64A**: `lr.w, sc.w, amoswap.w, amoadd.w, amoxor.w, amoand.w, amoor.w, amomin.w, amomax.w, amominu.w, amomaxu.w`\n  - **RV64A**: `lr.d, sc.d, amoswap.d, amoadd.d, amoxor.d, amoand.d, amoor.d, amomin.d, amomax.d, amominu.d, amomaxu.d`\n  - **Zicsr**: `csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci`\n\nFor details about RISC-V, refer to the ISA specification:\n[https://riscv.org/technical/specifications/](https://riscv.org/technical/specifications/).\n\n## Links to Resources and Similar Projects\n\n### Resources and Publications\n\n- Computer architectures pages at Czech Technical University in Prague [https://comparch.edu.cvut.cz/](https://comparch.edu.cvut.cz/)\n\n- Dupak, J.; Pisa, P.; Stepanovsky, M.; Koci, K. [QtRVSim – RISC-V Simulator for Computer Architectures Classes](https://comparch.edu.cvut.cz/publications/ewC2022-Dupak-Pisa-Stepanovsky-QtRvSim.pdf) In: [embedded world Conference 2022](https://events.weka-fachmedien.de/embedded-world-conference). Haar: WEKA FACHMEDIEN GmbH, 2022. p. 775-778. ISBN 978-3-645-50194-1. ([Slides](https://comparch.edu.cvut.cz/slides/ewc22-qtrvsim.pdf))\n\nPlease reference above article, if you use QtRvSim in education or research related materials and publications.\n\n- [FEE CTU - B35APO - Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b35apo)\n  - Undergraduate computer architecture class materials (\n    Czech) ([English](https://cw.fel.cvut.cz/wiki/courses/b35apo/en/start))\n- [FEE CTU - B4M35PAP - Advanced Computer Architectures](https://cw.fel.cvut.cz/wiki/courses/b4m35pap/start)\n  - Graduate computer architecture class materials (Czech/English)\n- [Graphical RISC-V Architecture Simulator - Memory Model and Project Management](https://dspace.cvut.cz/bitstream/handle/10467/94446/F3-BP-2021-Dupak-Jakub-thesis.pdf)\n  - Jakub Dupak's thesis\n  - Documents 2020-2021 QtMips and QtRvSim development\n- [Graphical CPU Simulator with Cache Visualization](https://dspace.cvut.cz/bitstream/handle/10467/76764/F3-DP-2018-Koci-Karel-diploma.pdf)\n  - Karel Koci's thesis\n  - Documents initial QtMips development\n\n### Projects\n\n- **QtMips** - MIPS predecessor of this simulator [https://github.com/cvut/QtMips/](https://github.com/cvut/QtMips/)\n\n- **RARS** - RISC-V Assembler and Runtime\n  Simulator [https://github.com/TheThirdOne/rars](https://github.com/TheThirdOne/rars)\n\n## Copyright\n\n- Copyright (c) 2017-2019 Karel Koci \u003ccynerd@email.cz\u003e\n- Copyright (c) 2019-2025 Pavel Pisa \u003cpisa@cmp.felk.cvut.cz\u003e\n- Copyright (c) 2020-2025 Jakub Dupak \u003cdev@jakubdupak.com\u003e\n- Copyright (c) 2020-2021 Max Hollmann \u003chollmmax@fel.cvut.cz\u003e\n\n## License\n\nThis project is licensed under `GPL-3.0-or-later`. The full text of the license is in the [LICENSE](LICENSE) file. The\nlicense applies to all files except for directories named `external` and files in them. Files in external directories\nhave a separate license compatible with the projects license.\n\n\u003e This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.\n\u003e\n\u003e This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.\n\u003e\n\u003e You should have received a copy of the GNU General Public License along with this program. If not, see [https://www.gnu.org/licenses/](https://www.gnu.org/licenses/).\n\n![Faculty of Electrical Engineering](./data/ctu/logo-fee.svg) ![Faculty of Information Technology](./data/ctu/logo-fit.svg) ![Czech Technical University](./data/ctu/logo-ctu.svg)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcvut%2Fqtrvsim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcvut%2Fqtrvsim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcvut%2Fqtrvsim/lists"}