{"id":15026115,"url":"https://github.com/cyring/corefreq","last_synced_at":"2025-05-14T06:14:43.263Z","repository":{"id":34032540,"uuid":"37792242","full_name":"cyring/CoreFreq","owner":"cyring","description":"CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.","archived":false,"fork":false,"pushed_at":"2025-05-12T15:14:36.000Z","size":8345,"stargazers_count":2076,"open_issues_count":3,"forks_count":135,"subscribers_count":57,"default_branch":"master","last_synced_at":"2025-05-12T16:31:34.740Z","etag":null,"topics":["aarch64","amd","arm64","cpu-cache","cpu-monitoring","cpu-temperature","cpu-topology","cpuid","cpuinfo","ddr","intel","multi-core","overclocking","powerpc","powerpc64","process-monitor","processor","ram-info","tuning","xeon"],"latest_commit_sha":null,"homepage":"https://www.cyring.fr","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/cyring.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2015-06-21T01:22:28.000Z","updated_at":"2025-05-12T15:14:40.000Z","dependencies_parsed_at":"2023-09-24T11:31:35.105Z","dependency_job_id":"fea253f1-0762-49f4-98ab-df2a1ba13a04","html_url":"https://github.com/cyring/CoreFreq","commit_stats":null,"previous_names":[],"tags_count":61,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cyring%2FCoreFreq","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cyring%2FCoreFreq/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cyring%2FCoreFreq/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/cyring%2FCoreFreq/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/cyring","download_url":"https://codeload.github.com/cyring/CoreFreq/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254083959,"owners_count":22011905,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["aarch64","amd","arm64","cpu-cache","cpu-monitoring","cpu-temperature","cpu-topology","cpuid","cpuinfo","ddr","intel","multi-core","overclocking","powerpc","powerpc64","process-monitor","processor","ram-info","tuning","xeon"],"created_at":"2024-09-24T20:03:49.217Z","updated_at":"2025-05-14T06:14:43.256Z","avatar_url":"https://github.com/cyring.png","language":"C","readme":"# _CoreFreq_\n## Purpose\n_CoreFreq_, CPU monitoring software with BIOS like functionalities, is designed for the 64-bits Processors of architecture Intel Atom, Core2, Nehalem, SandyBridge and superiors; AMD Families from 0Fh ... up to 17h (Zen , Zen+ , Zen 2), 18h (Hygon Dhyana), 19h (Zen 3, Zen 3+, Zen 4, Zen 4c), 1Ah (Zen 5, Zen 5c); Arm A64  \n\n![alt text](http://blog.cyring.free.fr/images/CoreFreq_Top.gif \"CoreFreq Top\")\n\n_CoreFreq_ provides a framework to retrieve CPU data with a high degree of precision:\n\n* Core frequencies \u0026 ratios; SpeedStep (EIST), Turbo Boost, Hyper-Threading (HTT) and Base Clock\n* Performance counters including Time Stamp Counter (TSC), Unhalted Core Cycles (UCC), Unhalted Reference Cycles (URC)\n* Number of instructions per cycle or second, IPS, IPC, or CPI\n* CPU C-States C0 C1 C3 C6 C7 - C1E - Auto/UnDemotion of C1 C3\n* DTS Temperature and Tjunction Max, Thermal Monitoring TM1 TM2 state, Vcore\n* Topology map including Caches for boostrap \u0026 application CPU\n* Processor features, brand \u0026 architecture strings\n* In progress: Uncore, Memory Controller channels \u0026 geometry, DIMM timings,  \n  Stress tools, Power \u0026 Energy (RAPL, P-State, HWP, TDP), Overclocking, cpuidle \u0026 cpufreq driver, ClockSource, Mitigation Mechanisms  \n\n\nTo reach this goal, _CoreFreq_ implements a Linux Kernel module which employs the followings:\n\n* asm code to keep as near as possible the readings of the performance counters;\n* per-CPU, implements slab data memory and high-resolution timer;\n* compliant with suspend / resume and CPU Hot-Plug;\n* a shared memory to protect kernel from the user-space part of the software;\n* atomic synchronization of threads to avoid mutexes and deadlock.\n\n## Build \u0026 Run\n\n### Prerequisites\n\n**a-** _Intel only_: For a better accuracy, *disable* the Kernel *NMI Watchdog*  \n\nAdd the below [parameter](https://github.com/torvalds/linux/blob/master/Documentation/admin-guide/kernel-parameters.txt) in the kernel boot loader { [Grub](https://www.gnu.org/software/grub/manual/grub/grub.html#GNU_002fLinux), [SysLinux](https://wiki.syslinux.org/wiki/index.php?title=Config#APPEND) } ...  \n\n```\nnmi_watchdog=0\n```\n... and build with the fixed performance counters  \n```\nmake MSR_CORE_PERF_UC=MSR_CORE_PERF_FIXED_CTR1 MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2\n```\n\n**b-** _AMD and Intel_: Some Virtualization  \n\nVMs don't provide access to the registers that the _CoreFreq_ driver employs :  \n* Fixed Performance Counters \n* Model Specific Registers \n* PCI Registers \n\nHowever _CoreFreq_ is making use of the virtualized performance counter :  \n* HV_X64_MSR_VP_RUNTIME(0x40000010) \n\n**c-** Rendering  \n\nThe UI renders best with an ASCII console or a Xterm with VT100 support, ANSI **colors**; optionally transparency.  \nIf **bold** and **bright** colors are not rendered then use the following terminal options:  \n#### Ubuntu Terminal\nIn the Preferences - Colors tab, select `Show bold text in bright colors`  \n#### alacritty terminal\nUncomment and set `draw_bold_text_with_bright_colors: true` in `\u003cconfig-file\u003e`  \n#### SSH\nForce pseudo-terminal allocation. This option is used to execute a menu based application on a remote machine.  \n```sh\nssh -t corefreq-cli\n```\n\n### Dependencies\n* The Linux Kernel with a minimum version 3.3\n* The GNU C Library\n\n### Build\n1. Software needed:  \n* GNU C Compiler with GNU extensions\n* GNU Make tool\n* Linux Kernel Header files to build modules\n  * Mandatory : `CONFIG_MODULES, CONFIG_SMP, CONFIG_X86_MSR`\n  * Optionally: `CONFIG_HOTPLUG_CPU, CONFIG_CPU_IDLE, CONFIG_CPU_FREQ, CONFIG_PM_SLEEP, CONFIG_DMI, CONFIG_HAVE_NMI, CONFIG_XEN, CONFIG_AMD_NB, CONFIG_SCHED_MUQSS, CONFIG_SCHED_BMQ, CONFIG_SCHED_PDS, CONFIG_SCHED_ALT, CONFIG_SCHED_BORE, CONFIG_CACHY, CONFIG_ACPI, CONFIG_ACPI_CPPC_LIB`\n  * Forbidden : `CONFIG_TRIM_UNUSED_KSYMS`\n\n2. Clone the source code into a working directory.  \n```sh\ngit clone https://github.com/cyring/CoreFreq.git\n```\n\n3. Build the programs.  \n```sh\ncd CoreFreq\nmake -j\n```\n```console\n  CC [build/corefreqd.o]\n  CC [build/corefreqm.o]\n  CC [build/corefreq-cli.o]\n  CC [build/corefreq-ui.o]\n  CC [build/corefreq-cli-rsc.o]\n  CC [build/corefreq-cli-json.o]\n  CC [build/corefreq-cli-extra.o]\n  LD [build/corefreqd]\n  LD [build/corefreq-cli]\n  CC [M]  CoreFreq/build/module/corefreqk.o\n  LD [M]  CoreFreq/build/corefreqk.o\n  MODPOST CoreFreq/build/Module.symvers\n  CC [M]  CoreFreq/build/corefreqk.mod.o\n  LD [M]  CoreFreq/build/corefreqk.ko\n  BTF [M] CoreFreq/build/corefreqk.ko\n```\n4. (Optionally) Sign the driver\nIf module signature verification is enabled into Kernel, you will have to sign the `corefreqk.ko` driver.  \n* See [module-signing.rst](https://github.com/torvalds/linux/blob/master/Documentation/admin-guide/module-signing.rst) from the Kernel documentation\n* See the [Gentoo Wiki](https://wiki.gentoo.org/wiki/Signed_kernel_module_support#Manually_signing_modules)\n\n### Install\n\n#### Manual\n5. Copying _CoreFreq_ into the binaries directory  \n```sh\nmake install\n```\n\n#### Distribution package\n6. Although _CoreFreq_ is released in the ArchLinux AUR ; other sources of distribution may require to reload the systemd daemons:  \n```sh\nsystemctl daemon-reload\n```\n\n### Start\n\n7. When built from source code:\n\n* Load the kernel module, from current directory, as root.  \n```sh\ninsmod build/corefreqk.ko\n```\n* Start the daemon, as root.  \n```sh\n./build/corefreqd\n```\n* Start the client, as a user (_in another terminal or console_).  \n```sh\n./build/corefreq-cli\n```\n\n8. When manually installed or from a distribution package:  \n\n* Load the kernel module, as root.  \n```sh\nmodprobe corefreqk\n```\n* Start the daemon, as root.  \n```sh\nsystemctl start corefreqd\n```\n* Start the client, as a user.  \n```sh\ncorefreq-cli\n```\n\n### Stop\n\n9. Press \u003ckbd\u003eCtrl+x\u003c/kbd\u003e or \u003ckbd\u003eCtrl+c\u003c/kbd\u003e to stop the client.\n\n10. Press \u003ckbd\u003eCtrl+c\u003c/kbd\u003e to stop the daemon (in foreground) or kill its background job.\n\n11. Unload the kernel module  \n```sh\nrmmod corefreqk.ko\n```\n\n### Try\nDownload the _CoreFreq_ Live CD from the [Wiki](http://github.com/cyring/CoreFreq/wiki/Live-CD)  \n![alt text](http://blog.cyring.free.fr/images/CoreFreq_LiveCD_Step1.png \"CoreFreq for ArchLinux\")  \n\n## Screenshots\n### Linux kernel module\nUse `lsmod`, `dmesg` or `journalctl -k` to check if the module is started:  \n```console\nCoreFreq(14:30:-1): Processor [ 8F_71] Architecture [Zen2/Matisse] SMT [32/32]\n```\n\n### Daemon\n\n```console\nCoreFreq Daemon #.##.#  Copyright (C) 2015-2025 CYRIL COURTIAT\n\n  Processor [AMD Ryzen 9 3950X 16-Core Processor]\n  Architecture [Zen2/Matisse] 32/32 CPU Online.\n```\n\n### Client\n\nWithout arguments, the corefreq-cli program displays Top Monitoring  \n![alt text](http://blog.cyring.free.fr/images/CoreFreq_Tour_2017-12-06.gif \"CoreFreq UI\")  \n  _Remark_: Drawing will stall if the terminal width is lower than 80 columns, or its height is less than required.  \n\n* Memory Controller  \n\n![alt text](http://blog.cyring.free.fr/images/CoreFreq_MC.png \"IMC\")\n\n* With the option `-c`, the client traces counters  \n\n![alt text](http://blog.cyring.free.fr/images/CoreFreq_Counters.gif \"CoreFreq Counters\")\n\n* Using option `-m` corefreq-cli shows the CPU topology  \n\n![alt text](http://blog.cyring.free.fr/images/CoreFreq_Topology.png \"CoreFreq CPU \u0026 caches topology\")\n\n* With the option `-i` corefreq-cli traces the number of instructions per second / cycle  \n\n```\nCPU     IPS            IPC            CPI\n#00     0.000579/s     0.059728/c    16.742698/i\n#01     0.000334/s     0.150569/c     6.641471/i\n#02     0.000598/s     0.161326/c     6.198641/i\n#03     0.000294/s     0.233535/c     4.282013/i\n#04     0.000240/s     0.042931/c    23.293141/i\n#05     0.000284/s     0.158661/c     6.302765/i\n#06     0.000128/s     0.128031/c     7.810631/i\n#07     0.000088/s     0.150406/c     6.648674/i\n```\n\n* Use the option `-s` to show the Processor information (BSP)  \n\n![alt text](http://blog.cyring.free.fr/images/CoreFreq_SysInfo.png \"CoreFreq System Info\")\n\n## ArchLinux\n* [![corefreq](https://img.shields.io/aur/version/corefreq-dkms?style=flat-square)](https://aur.archlinux.org/pkgbase/corefreq/) follows released tags\n\n## Gentoo Linux\n* In [GURU overlay](https://wiki.gentoo.org/wiki/Project:GURU/Information_for_End_Users) CoreFreq [package](https://github.com/gentoo/guru/tree/master/sys-apps/corefreq), please contact [vitaly-zdanevich](https://github.com/vitaly-zdanevich)  \n\n## Debian, Ubuntu, TUXEDO\n * Installing the DKMS package will pull the Kernel development packages  \n```sh\napt install dkms\n```\n * Or install the kernel development prerequisites.  \n```sh\napt list git build-essential gawk fakeroot linux-headers*\n```\n\n## Red Hat, CentOS\n * Development packages prerequisites.  \n```sh\nyum install kernel-devel\nyum group install \"Development Tools\"\n```\n\n## AlmaLinux, Rocky Linux\n```sh\n## as root, install kernel development package and dependencies\ndnf --assumeyes install kernel-devel gcc make git bc\n```\n```sh\n## as a User, build CoreFreq\ncd CoreFreq\nmake -j\n```\n```sh\n## as root, install the binaries\nmake install\n## and start Driver and Daemon\nmodprobe corefreqk\ncorefreqd\n```\n```sh\n## as a User, start the Client\ncorefreq-cli\n```\n```sh\n## Terminate Client, Daemon and unload Driver as root\nmodprobe -r corefreqk\n## Proceed to uninstallation as root\ncd CoreFreq\nmake uninstall\n```\n\n## openSUSE\n * Packages\n1. [CoreFreq](https://software.opensuse.org/package/CoreFreq) official release\n2. [CoreFreq-kmp-default](https://software.opensuse.org/package/CoreFreq-kmp-default) \n\n## ProxMox\n\nInstall Tools\n```sh\napt-get install build-essential dkms git libpthread-stubs0-dev\n```\n\nInstall headers related to your kernel\n```sh\napt install pve-headers-`uname -r`\n\ngit clone https://github.com/cyring/CoreFreq.git\ncd CoreFreq \u0026\u0026 make\n```\n\nInstall the module in the system, refresh it and start it\n```sh\nmake install\ndepmod\nmodprobe corefreqk\nsystemctl start corefreqd\n```\n\n## Unraid\n * Plugin\n1. `corefreq.plg` from [ich777/unraid-corefreq](https://github.com/ich777/unraid-corefreq)\n2. Based on latest developments, please contact [ich777](https://github.com/ich777)  \n\n## Alpine\n```sh\n## Install the kernel development packages\napk add alpine-sdk sed installkernel bc nawk diffutils findutils pahole openssl-dev python3 linux-virt linux-virt-dev\n```\n\n## Chimera\n```sh\n## Install the kernel development packages\ndoas apk add git ckms gmake clang linux-headers linux-lts-devel\n## Add the CoreFreq directory containing the ckms.ini file\ndoas ckms add CoreFreq/\n## Build the CoreFreq version M.m.r\ndoas ckms build corefreqk=M.m.r\n## Or manually if using the Clang compiler\ngmake CC=clang\n```\n\n## [Clear Linux](https://github.com/cyring/CoreFreq/wiki/CoreFreq-for-Clear-Linux)\n\n## [Buildroot](https://github.com/cyring/CoreFreq-buildroot)\n\n## Q\u0026A\n* Q: How many CPUs are supported by _CoreFreq_ ?  \n\n  A: Up to 1024 CPUs can be built using the `make` `CORE_COUNT` option.  256 as a default.  \n\n* Q: Turbo Technology is activated however CPUs don't reach those frequencies ?  \n\n* Q: The CPU ratio does not go above its minimum value ?  \n\n* Q: The UI shows erratic counters values !  \n\n  A: In the kernel boot command argument line, *disable the NMI Watchdog*  \n`nmi_watchdog=0`  \n\n\n* Q: The Processor does not enter the C-States ?  \n\n  A1: Check if at least one Idle driver is running.  \n  Accordingly to the Processor specs, provide a max_cstate value in the kernel argument as below.  \n`intel_idle.max_cstate=value`  \n\n  A2: _CoreFreq_ can also register itself as a cpuidle driver.  \n  This time, any idle driver will have to be blacklisted in the kernel command line; such as:  \n`modprobe.blacklist=intel_cstate idle=halt intel_idle.max_cstate=0`  \n  Start the _CoreFreq_ driver with the `Register_CPU_Idle` parameter:  \n`insmod corefreqk.ko Register_CPU_Idle=1`  \n\n\n* Q: The _CoreFreq_ UI refreshes itself slowly, with a delay after the actual CPUs usage ?  \n\n  A: The sampling time to read the counters can be reduced or increased using a _CoreFreq_ module argument:  \n`insmod corefreqk.ko SleepInterval=value`  \n  where `\u003cvalue\u003e` is supplied in milliseconds between a minimum of 100 ms and a maximum of 4500 ms. 1000 ms is the default value.  \n\n\n* Q: The base clock reports a wrong frequency value ?  \n\n  A: _CoreFreq_ uses various algorithms to estimate the base clock.  \n  \n  1. The delta of two TimeStamp counters during a defined interval  \n  2. The value provided in the Processor brand string divided by the maximum ratio (without Turbo)  \n  3. A static value advertised by the manufacturer specs.  \n  4. The MSR_FSB_FREQ bits provided with the Core, Core2 and Atom architectures.  \n\n  The _CoreFreq_ module can be started as follow to ignore the first algorithm (frequency estimation):  \n`insmod corefreqk.ko AutoClock=0`  \n\n  _Remark: algorithms # 2, 3 and 4 will not return any under/over-clock frequency._  \n\n\n* Q: The CPU temperature is wrong ?  \n\n  A: _CoreFreq_ employs two MSR registers to calculate the temperature.  \n`MSR_IA32_TEMPERATURE_TARGET - MSR_IA32_THERM_STATUS [DTS]`  \n\n  _Remark_: if the MSR_IA32_TEMPERATURE_TARGET is not provided by the Processor, a default value of 100 degree Celsius is considered as a target.  \n\n\n* Q: The menu option \"Memory Controller\" does not open any window ?  \n\n  A: Although Uncore and IMC features are under development, they can be activated with the Experimental driver argument:  \n`insmod corefreqk.ko Experimental=1`  \n\n\n* Q: The Instructions and PMC0 counters are stuck to zero ?  \n* Q: The Daemon crashes whenever its stress tools are executing !  \n\n  A: The `PCE` bit of control register `CR4` allows RDPMC in ring `3`  \n`echo \"2\" \u003e /sys/devices/cpu/rdpmc`  \n  or using systemd, create file `/etc/tmpfiles.d/boot.conf` and add line:  \n  `w /sys/devices/cpu/rdpmc - - - - 2`  \n\n  Next, load the driver with the `RDPMC_Enable` argument to override the `CR4` register:  \n`insmod corefreqk.ko RDPMC_Enable=1`  \n\n\n* Q: How to solely control the P-States or the HWP Performance States ?  \n\n  A1: Without the Kernel `cpufreq` framework (aka `CONFIG_CPU_FREQ`), _CoreFreq_ will take the full control over P-States.  \n  This allow the User to select a _capped_ frequency from the UI, either per Core, either for the whole Processor.  \n\n  A2: With `cpufreq` built into Kernel, allow _CoreFreq_ to register as a cpufreq driver.  \n  In the Kernel boot command line, blacklist any P-state driver; such as:  \n`modprobe.blacklist=acpi_cpufreq,pcc_cpufreq intel_pstate=disable`  \n\n  * hardware CPPC (MSR registers)  \n`initcall_blacklist=amd_pstate_init`\n\n  * firmware CPPC (ACPI registers)  \n`amd_pstate.shared_mem=0` and/or `initcall_blacklist=acpi_cpufreq_init`\n\n 3. load the _CoreFreq_ driver with its `Register_CPU_Freq` parameter:  \n`insmod corefreqk.ko Register_CPU_Freq=1`  \n\n* Q: Governor is missing in Kernel window even after a successful registration.  \n\n  A: When Registrations are done through the UI, they have  to be done in the following order:  \n\n 1. Clock Source  \n 2. Governor driver  \n 3. CPU-FREQ driver  \n 4. CPU-IDLE driver  \n 5. CPU-IDLE route  \n\n* Q: The CPU freezes or the System crashes.  \n\n  A1: Changing the `Max` ratio frequency (aka P0 P-State) makes the Kernel TSC clock source unstable.  \n  1. Boot the Kernel with these command line parameters `notsc nowatchdog`  \n  2. Optionally, build the _CoreFreq_ driver with its `udelay()` TSC implementation  \n`make DELAY_TSC=1`  \n  3. Allow _CoreFreq_ to register a new TSC clock source using driver arguments:  \n`insmod corefreqk.ko TurboBoost_Enable=0 Register_ClockSource=1`  \n  4. Switch the current system clock source to `corefreq`  \n`echo \"corefreq\" \u003e /sys/devices/system/clocksource/clocksource0/current_clocksource`  \n\n  A2: `[AMD][Zen]` SMU:  \n  _CoreFreq_ CPU monitoring loops are executed in an interrupt context where any blocking call like Mutex will freeze the kernel.  \n  As a recommendation, **make sure no other SMU driver is running**.  \n\n  A3: This Processor is not or partially implemented in _CoreFreq_.  \n  Please open an issue in the [CPU support](https://github.com/cyring/CoreFreq/wiki/CPU-support) Wiki page.  \n\n* Q: No voltage is showing up with Nehalem or Westmere processors ?  \n\n  A: Build _CoreFreq_ as below if one of those chips is present:  \n`make HWM_CHIPSET=W83627`  \n  or  \n`make HWM_CHIPSET=IT8720`  \n\n* Q: `[AMD][Zen]` How to read the idle states ?  \n\n  A: As a workarround to the missing documentation of the hardware counters, _CoreFreq_ implements virtual counters based on the TSC  \n  Those VPMC are estimated each time the Kernel is entering an idle state level.  \n  The prerequisities are:  \n  1. Boot the Kernel without its idle drivers and no `TSC` default clock source set  \n  `modprobe.blacklist=acpi_cpufreq idle=halt tsc=unstable`  \n  2. Build _CoreFreq_ with its `TSC` implementation  \n  `make DELAY_TSC=1`\n  3. Load and **register** the _CoreFreq_ kernel module as the system handler  \n  `insmod corefreqk.ko Register_ClockSource=1 Register_Governor=1 Register_CPU_Freq=1 Register_CPU_Idle=1 Idle_Route=1`  \n  4. Define _CoreFreq_ as the System clock source  \n  `echo \"corefreq\" \u003e /sys/devices/system/clocksource/clocksource0/current_clocksource`  \n  5. Start the Daemon then the Client  \n![alt text](http://blog.cyring.free.fr/images/CoreFreq_Zen_VPMC.png \"CoreFreq for AMD Zen\")  \n  - The registration is confirmed into the `Settings` window  \n  - The idle limit can be changed at any time in the `Kernel` window  \n![alt text](http://blog.cyring.free.fr/images/CoreFreq_Idle_Limit.png \"Idle Limit\")  \n\n* Q: How does _CoreFreq_ work with `cgroups` ?  \n\n  A: The Daemon and the Client have to run in the `root cgroups cpugroup`, by using these commands:  \n  ( _thanks to Conne Beest @connebeest_ )  \n`cgexec -g cpuset:/ ./corefreqd`  \n`cgexec -g cpuset:/ ./cofrefreq-cli`  \n\n* Q: How to enable transparency in the User Interface ?  \n\n  A: Transparency is a build option invoked by the compilation directive `UI_TRANSPARENCY`  \n  1. Build the project with `UI_TRANSPARENCY` enabled  \n`make UI_TRANSPARENCY=1`\n  2. Start the Client with one of its transparency compatible colors theme  \n`corefreq-cli -OE 2 -t`  \n  3. Or switch to that theme from `Menu \u003e Theme`, shortcut [`E`]  \n\n* Q: How to screenshot the UI ?  \n\n  A: Press `[Ctrl]+[p]` to save the screen to a rich ascii file.  Use the `cat` or `less -R` command to view the file saved with an `asc` extension.  \n\n* Q: How to record the UI ?  \n\n  A: Press `[Alt]+[p]` to record the screen for the duration set in Settings. A compatible [asciinema](https://github.com/asciinema/asciinema) file is saved in the current directory with a `cast` extension.  \n\n* Q: What are the build options for _CoreFreq_ ?  \n\n  A: Enter `make help` to display them:  \n\n```\no---------------------------------------------------------------o\n|  make [all] [clean] [info] [help] [install] [module-install]  |\n|                                                               |\n|  V=\u003cn\u003e                                                        |\n|    where \u003cn\u003e is the verbose build level                       |\n|                                                               |\n|  CC=\u003cCOMPILER\u003e                                                |\n|    where \u003cCOMPILER\u003e is cc, gcc, clang                         |\n|                                                               |\n|  WARNING=\u003cARG\u003e                                                |\n|    where default argument is -Wall                            |\n|                                                               |\n|  KERNELDIR=\u003cPATH\u003e                                             |\n|    where \u003cPATH\u003e is the Kernel source directory                |\n|                                                               |\n|  CORE_COUNT=\u003cN\u003e                                               |\n|    where \u003cN\u003e is 64, 128, 256, 512 or 1024 builtin CPU         |\n|                                                               |\n|  LEGACY=\u003cL\u003e                                                   |\n|    where level \u003cL\u003e                                            |\n|    1: assembly level restriction such as CMPXCHG16            |\n|                                                               |\n|  UBENCH=\u003cN\u003e                                                   |\n|    where \u003cN\u003e is 0 to disable or 1 to enable micro-benchmark   |\n|                                                               |\n|  TASK_ORDER=\u003cN\u003e                                               |\n|    where \u003cN\u003e is the memory page unit of kernel allocation     |\n|                                                               |\n|  FEAT_DBG=\u003cN\u003e                                                 |\n|    where \u003cN\u003e is 0 or N for FEATURE DEBUG level                |\n|    3: XMM assembly in RING operations                         |\n|                                                               |\n|  DELAY_TSC=\u003cN\u003e                                                |\n|    where \u003cN\u003e is 1 to build a TSC implementation of udelay()   |\n|                                                               |\n|  OPTIM_LVL=\u003cN\u003e                                                |\n|    where \u003cN\u003e is 0, 1, 2 or 3 of the OPTIMIZATION level        |\n|                                                               |\n|  MAX_FREQ_HZ=\u003cfreq\u003e                                           |\n|    where \u003cfreq\u003e is at least 4850000000 Hz                     |\n|                                                               |\n|  HWM_CHIPSET=\u003cchipset\u003e                                        |\n|    where \u003cchipset\u003e is W83627; IT8720; AMD_VCO or COMPATIBLE   |\n|                                                               |\n|  Performance Counters:                                        |\n|    -------------------------------------------------------    |\n|   |     MSR_CORE_PERF_UCC     |     MSR_CORE_PERF_URC     |   |\n|   |----------- REG -----------|----------- REG -----------|   |\n|   | MSR_IA32_APERF            |  MSR_IA32_MPERF           |   |\n|   | MSR_CORE_PERF_FIXED_CTR1  |  MSR_CORE_PERF_FIXED_CTR2 |   |\n|   | MSR_PPERF                 |  MSR_PPERF                |   |\n|   | MSR_AMD_F17H_APERF        |  MSR_AMD_F17H_MPERF       |   |\n|    -------------------------------------------------------    |\n|                                                               |\n|  Architectural Counters:                                      |\n|    -------------------------------------------------------    |\n|   |           Intel           |            AMD            |   |\n|   |----------- REG -----------|----------- REG -----------|   |\n|   |       ARCH_PMC=PCU        |      ARCH_PMC=L3          |   |\n|   |                           |      ARCH_PMC=PERF        |   |\n|   |                           |      ARCH_PMC=UMC         |   |\n|    -------------------------------------------------------    |\n|                                                               |\n|  User Interface Layout:                                       |\n|    NO_HEADER=\u003cF\u003e  NO_FOOTER=\u003cF\u003e  NO_UPPER=\u003cF\u003e  NO_LOWER=\u003cF\u003e   |\n|      when \u003cF\u003e is 1: don't build and display this area part    |\n|    UI_TRANSPARENCY=\u003cF\u003e                                        |\n|      when \u003cF\u003e is 1: build with background transparency        |\n|    UI_RULER_MINIMUM=\u003cN\u003e, UI_RULER_MAXIMUM=\u003cN\u003e                 |\n|      set ruler left or right bound to \u003cN\u003e frequency ratio     |\n|                                                               |\n|  Example:                                                     |\n|    make CC=gcc OPTIM_LVL=3 FEAT_DBG=1 ARCH_PMC=PCU            |\n|         MSR_CORE_PERF_UCC=MSR_CORE_PERF_FIXED_CTR1            |\n|         MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2            |\n|         HWM_CHIPSET=W83627 MAX_FREQ_HZ=5350000000             |\n|         CORE_COUNT=1024 NO_FOOTER=1 NO_UPPER=1                |\no---------------------------------------------------------------o\n```\n\n* Q: What are the parameters of the _CoreFreq_ driver ?  \n\n  A: Use the `modinfo` command to list them:  \n\n```\n$ modinfo corefreqk.ko\nparm:           ArchID:Force an architecture (ID) (int)\nparm:           AutoClock:Estimate Clock Frequency 0:Spec; 1:Once; 2:Auto (int)\nparm:           SleepInterval:Timer interval (ms) (uint)\nparm:           TickInterval:System requested interval (ms) (uint)\nparm:           Experimental:Enable features under development (int)\nparm:           CPU_Count:-1:Kernel(default); 0:Hardware; \u003e0: User value (int)\nparm:           Target_Ratio_Unlock:1:Target Ratio Unlock; 0:Lock (short)\nparm:           Clock_Ratio_Unlock:1:MinRatio; 2:MaxRatio; 3:Both Unlock (short)\nparm:           Turbo_Ratio_Unlock:1:Turbo Ratio Unlock; 0:Lock (short)\nparm:           Uncore_Ratio_Unlock:1:Uncore Ratio Unlock; 0:Lock (short)\nparm:           ServiceProcessor:Select a CPU to run services with (int)\nparm:           RDPMC_Enable:Enable RDPMC bit in CR4 register (ushort)\nparm:           NMI_Disable:Disable the NMI Handler (ushort)\nparm:           Override_SubCstate:Override Sub C-States (array of ushort)\nparm:           PkgCStateLimit:Package C-State Limit (short)\nparm:           IOMWAIT_Enable:I/O MWAIT Redirection Enable (short)\nparm:           CStateIORedir:Power Mgmt IO Redirection C-State (short)\nparm:           Config_TDP_Level:Config TDP Control Level (short)\nparm:           Custom_TDP_Offset:TDP Limit Offset (watt) (array of short)\nparm:           Activate_TDP_Limit:Activate TDP Limiting (array of short)\nparm:           Activate_TDP_Clamp:Activate TDP Clamping (array of short)\nparm:           Custom_TDC_Offset:TDC Limit Offset (amp) (short)\nparm:           Activate_TDC_Limit:Activate TDC Limiting (short)\nparm:           L1_HW_PREFETCH_Disable:Disable L1 HW Prefetcher (short)\nparm:           L1_HW_IP_PREFETCH_Disable:Disable L1 HW IP Prefetcher (short)\nparm:           L1_NPP_PREFETCH_Disable:Disable L1 NPP Prefetcher (short)\nparm:           L1_Scrubbing_Enable:Enable L1 Scrubbing (short)\nparm:           L2_HW_PREFETCH_Disable:Disable L2 HW Prefetcher (short)\nparm:           L2_HW_CL_PREFETCH_Disable:Disable L2 HW CL Prefetcher (short)\nparm:           L2_AMP_PREFETCH_Disable:Adaptive Multipath Probability (short)\nparm:           L2_NLP_PREFETCH_Disable:Disable L2 NLP Prefetcher (short)\nparm:           L1_STRIDE_PREFETCH_Disable:Disable L1 Stride Prefetcher (short)\nparm:           L1_REGION_PREFETCH_Disable:Disable L1 Region Prefetcher (short)\nparm:           L1_BURST_PREFETCH_Disable:Disable L1 Burst Prefetcher (short)\nparm:           L2_STREAM_PREFETCH_Disable:Disable L2 Stream Prefetcher (short)\nparm:           L2_UPDOWN_PREFETCH_Disable:Disable L2 Up/Down Prefetcher (short)\nparm:           LLC_Streamer_Disable:Disable LLC Streamer (short)\nparm:           SpeedStep_Enable:Enable SpeedStep (short)\nparm:           C1E_Enable:Enable SpeedStep C1E (short)\nparm:           TurboBoost_Enable:Enable Turbo Boost (array of short)\nparm:           C3A_Enable:Enable C3 Auto Demotion (short)\nparm:           C1A_Enable:Enable C3 Auto Demotion (short)\nparm:           C3U_Enable:Enable C3 UnDemotion (short)\nparm:           C1U_Enable:Enable C1 UnDemotion (short)\nparm:           C2U_Enable:Enable C2 UnDemotion (short)\nparm:           CC6_Enable:Enable Core C6 State (short)\nparm:           PC6_Enable:Enable Package C6 State (short)\nparm:           ODCM_Enable:Enable On-Demand Clock Modulation (short)\nparm:           ODCM_DutyCycle:ODCM DutyCycle [0-7] | [0-14] (short)\nparm:           PowerMGMT_Unlock:Unlock Power Management (short)\nparm:           PowerPolicy:Power Policy Preference [0-15] (short)\nparm:           Turbo_Activation_Ratio:Turbo Activation Ratio (short)\nparm:           PState_FID:P-State Frequency Id (int)\nparm:           PState_VID:P-State Voltage Id (int)\nparm:           Ratio_Boost:Turbo Boost Frequency ratios (array of int)\nparm:           Ratio_PPC:Target Performance ratio (int)\nparm:           HWP_Enable:Hardware-Controlled Performance States (short)\nparm:           HWP_EPP:Energy Performance Preference (short)\nparm:           Ratio_HWP:Hardware-Controlled Performance ratios (array of int)\nparm:           HDC_Enable:Hardware Duty Cycling (short)\nparm:           EEO_Disable:Disable Energy Efficiency Optimization (short)\nparm:           R2H_Disable:Disable Race to Halt (short)\nparm:           Clear_Events:Clear Thermal and Power Events (ullong)\nparm:           ThermalOffset:Thermal Offset (short)\nparm:           ThermalScope:[0:None; 1:SMT; 2:Core; 3:Package] (int)\nparm:           VoltageScope:[0:None; 1:SMT; 2:Core; 3:Package] (int)\nparm:           PowerScope:[0:None; 1:SMT; 2:Core; 3:Package] (int)\nparm:           Register_CPU_Idle:Register the Kernel cpuidle driver (short)\nparm:           Register_CPU_Freq:Register the Kernel cpufreq driver (short)\nparm:           Register_Governor:Register the Kernel governor (short)\nparm:           Register_ClockSource:Register Clock Source driver (short)\nparm:           Idle_Route:[0:Default; 1:I/O; 2:HALT; 3:MWAIT] (short)\nparm:           Mech_IBRS:Mitigation Mechanism IBRS (short)\nparm:           Mech_STIBP:Mitigation Mechanism STIBP (short)\nparm:           Mech_SSBD:Mitigation Mechanism SSBD (short)\nparm:           Mech_IBPB:Mitigation Mechanism IBPB (short)\nparm:           Mech_SBPB:Mitigation Mechanism SBPB (short)\nparm:           Mech_L1D_FLUSH:Mitigation Mechanism Cache L1D Flush (short)\nparm:           Mech_PSFD:Mitigation Mechanism PSFD (short)\nparm:           Mech_BTC_NOBR:Mitigation Mechanism BTC-NOBR (short)\nparm:           Mech_XPROC_LEAK:Mitigation Mech. Cross Processor Leak (short)\nparm:           Mech_AGENPICK:Mitigation Mech. LsCfgDisAgenPick (short)\nparm:           WDT_Enable:Watchdog Hardware Timer (short)\nparm:           HSMP_Attempt:Attempt the HSMP interface (short)\n```  \n\n## Arm [AArch64]\n### Screenshots\n\n![alt text](http://blog.cyring.free.fr/images/CoreFreq_RK3588.png \"RK3588 OPi 5 Plus\")\n\n### Q\u0026A\n\n* Q: Counters are stuck to zero  \n\n  A: Add parameter `nohlt` to the kernel boot command line.  \n\n----\n\n## Algorithm\n![alt text](http://blog.cyring.free.fr/images/CoreFreq-algorithm.png \"CoreFreq algorithm\")\n\n# About\n[CyrIng](https://github.com/cyring)\n\nCopyright (C) 2015-2025 CYRIL COURTIAT  \n -------\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcyring%2Fcorefreq","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcyring%2Fcorefreq","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcyring%2Fcorefreq/lists"}