{"id":13994635,"url":"https://github.com/d0iasm/rvemu-for-book","last_synced_at":"2026-02-09T03:34:21.689Z","repository":{"id":39373003,"uuid":"254639934","full_name":"d0iasm/rvemu-for-book","owner":"d0iasm","description":"Reference implementation for the book \"Writing a RISC-V Emulator in Rust\".","archived":false,"fork":false,"pushed_at":"2022-08-11T05:20:51.000Z","size":455,"stargazers_count":385,"open_issues_count":3,"forks_count":24,"subscribers_count":22,"default_branch":"main","last_synced_at":"2025-07-22T20:44:33.778Z","etag":null,"topics":["emulator","riscv","riscv-emulator","rust","xv6"],"latest_commit_sha":null,"homepage":"http://book.rvemu.app/","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/d0iasm.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-04-10T13:21:37.000Z","updated_at":"2025-07-19T09:43:08.000Z","dependencies_parsed_at":"2022-08-09T14:48:33.414Z","dependency_job_id":null,"html_url":"https://github.com/d0iasm/rvemu-for-book","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/d0iasm/rvemu-for-book","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/d0iasm%2Frvemu-for-book","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/d0iasm%2Frvemu-for-book/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/d0iasm%2Frvemu-for-book/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/d0iasm%2Frvemu-for-book/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/d0iasm","download_url":"https://codeload.github.com/d0iasm/rvemu-for-book/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/d0iasm%2Frvemu-for-book/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29255602,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-09T03:07:45.136Z","status":"ssl_error","status_checked_at":"2026-02-09T03:07:24.123Z","response_time":56,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["emulator","riscv","riscv-emulator","rust","xv6"],"created_at":"2024-08-09T14:03:00.370Z","updated_at":"2026-02-09T03:34:21.673Z","avatar_url":"https://github.com/d0iasm.png","language":"Rust","funding_links":[],"categories":["Rust"],"sub_categories":[],"readme":"# rvemu-for-book\nReference implementation of [the book](https://book.rvemu.app/), *Writing a RISC-V Emulator from Scratch in 10 Steps*. The goal of this code and the book is runnning [xv6](https://github.com/mit-pdos/xv6-riscv) in our emulator.\n\nThis is based on original RISC-V emulator [rvemu](https://github.com/d0iasm/rvemu) in Rust.\n\n## How to run xv6\n```\n$ cd step10 // move to the step10 directory\n$ cargo run ./xv6-kernel.bin ./xv6-fs.img\n```\n\n![demo.png](https://raw.githubusercontent.com/d0iasm/rvemu-for-book/master/demo.png)\n\n## Step to implement a RISC-V emulator\nSee https://book.rvemu.app/\n- Step 1: Setup and Implement Two Instructions\n- Step 2: RV64I Base Integer Instruction Set\n- Step 3: Control and Status Registers\n- Step 4: Privileged Instruction Set\n- Step 5: Exceptions\n- Step 6: UART (a universal asynchronous receiver-transmitter)\n- Step 7: PLIC (a platform-level interrupt controller) and CLINT (a core-local interrupter)\n- Step 8: Interrupts\n- Step 9: Virtio\n- Step 10: Virtual Memory System\n\nEach step has a `diff` file generated by `diff -x target -r step\u003cprevious\u003e step\u003ccurrent\u003e \u003e diff_\u003cprevious\u003e_\u003ccurrent\u003e`.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fd0iasm%2Frvemu-for-book","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fd0iasm%2Frvemu-for-book","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fd0iasm%2Frvemu-for-book/lists"}