{"id":15100835,"url":"https://github.com/davidar/fpgatoy","last_synced_at":"2026-01-07T15:40:07.996Z","repository":{"id":229260431,"uuid":"776253373","full_name":"davidar/fpgatoy","owner":"davidar","description":"Shadertoy for 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fpgatoy\n\nThis is a simple framework for running Shadertoy-style \"shaders\" on an FPGA, synthesised directly as a logic circuit without any CPU or GPU.\nIt operates by [\"racing the beam\"](https://tomverbeure.github.io/rtl/2018/11/26/Racing-the-Beam-Ray-Tracer.html),\ngenerating pixel values just in time to be sent out in the HDMI signal, without any intermediate framebuffer.\n\n![](img/human_shader.jpeg)\n\n\u003cimg src=\"img/bands.png\" width=\"32%\" /\u003e \u003cimg src=\"img/hedgehog.png\" width=\"32%\" /\u003e \u003cimg src=\"img/rbzero.png\" width=\"32%\" /\u003e\n\u003cimg src=\"img/rt.png\" width=\"32%\" /\u003e \u003cimg src=\"img/silice_vga_msponge.png\" width=\"32%\" /\u003e \u003cimg src=\"img/vgatestsrc.png\" width=\"32%\" /\u003e\n\n## Hardware\n\nI'm using a Colorlight i9, with [Muse Lab's development board](https://tomverbeure.github.io/2021/01/22/The-Colorlight-i5-as-FPGA-development-board.html).\nThis is the best value FPGA board I've found — it provides 45k LUTs (almost double the 25k LUTs in the i5 version) and can be purchased for less than 50 USD.\n\n![](img/colorlight_i9.jpeg)\n\nHowever, thanks the the abstractions provided by [LiteX-Boards](https://github.com/litex-hub/litex-boards), it should be trivial to port to any of the other 100+ supported FPGA platforms.\n\nOne thing to keep in mind is that the clock reset generators (CRGs) provided by `litex_boards.targets` don't follow a consistent abstraction,\nwith most of them hardcoding the HDMI video clocks for a specific resolution and framerate.\nI've [patched](https://github.com/davidar/litex-boards/commit/6acd4fe39d7435a99625aedee195cffe4427d781) the `colorlight_i5` target to expose the pixel clock frequency.\n\n## Software\n\n- [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)\n- [LiteX](https://github.com/enjoy-digital/litex)\n- remember to [setup udev rules](https://github.com/adamgreig/ecpdap/tree/master/drivers)\n\nIf using WSL2:\n- [usbipd](https://github.com/dorssel/usbipd-win)\n- [kernel with `CONFIG_USB_HIDDEV` enabled](https://github.com/microsoft/WSL2-Linux-Kernel/releases/tag/linux-msft-wsl-5.15.150.1)\n\nTo build and load a simple example shader, just run `./example.py` from the `src/` directory.\n\nMost of the examples run in simulation by default, but you can run them on the FPGA by\ncommenting out the `@fpgatoy.SimSoC` line and uncommenting `@fpgatoy.MySoC`.\nThis is the class that you'll need to modify to support different hardware,\nfor the colorlight it looks like this:\n\n```py\nclass MySoC(BaseSoC):\n    def __init__(self, main_image):\n        self._sys_clk_freq = int(25e6)\n        self._platform = colorlight_i5.Platform(\"i9\", \"7.2\")\n        self.crg = colorlight_i5_CRG(\n            self._platform, self._sys_clk_freq, with_video_pll=True, pix_clk=25e6\n        )\n        BaseSoC.__init__(self, main_image, \"hdmi\")\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdavidar%2Ffpgatoy","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdavidar%2Ffpgatoy","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdavidar%2Ffpgatoy/lists"}