{"id":51462616,"url":"https://github.com/davidclawson/gw1n2-apicula","last_synced_at":"2026-07-06T07:01:21.456Z","repository":{"id":364808225,"uuid":"1269289859","full_name":"DavidClawson/gw1n2-apicula","owner":"DavidClawson","description":"Open-source RE toward Gowin GW1N-2 (IDCODE 0x0120681B) bitstream support in Project Apicula — for the FNIRSI 2C53T scope's FPGA.","archived":false,"fork":false,"pushed_at":"2026-06-14T14:54:45.000Z","size":541,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-06-14T16:43:58.597Z","etag":null,"topics":["apicula","bitstream","chipdb","fnirsi","fpga","gowin","gowin-fpga","gw1n","gw1n-2","hardware-reverse-engineering","nextpnr","open-source-hardware","oscilloscope","reverse-engineering","yosys"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/DavidClawson.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2026-06-14T14:30:41.000Z","updated_at":"2026-06-14T14:54:50.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/DavidClawson/gw1n2-apicula","commit_stats":null,"previous_names":["davidclawson/gw1n2-apicula"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/DavidClawson/gw1n2-apicula","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DavidClawson%2Fgw1n2-apicula","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DavidClawson%2Fgw1n2-apicula/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DavidClawson%2Fgw1n2-apicula/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DavidClawson%2Fgw1n2-apicula/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/DavidClawson","download_url":"https://codeload.github.com/DavidClawson/gw1n2-apicula/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DavidClawson%2Fgw1n2-apicula/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":35180933,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-07-06T02:00:07.184Z","response_time":106,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["apicula","bitstream","chipdb","fnirsi","fpga","gowin","gowin-fpga","gw1n","gw1n-2","hardware-reverse-engineering","nextpnr","open-source-hardware","oscilloscope","reverse-engineering","yosys"],"created_at":"2026-07-06T07:01:19.581Z","updated_at":"2026-07-06T07:01:21.450Z","avatar_url":"https://github.com/DavidClawson.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# GW1N-2 Apicula Support\n\n**Open-source bitstream reverse-engineering to add the Gowin GW1N-2 (IDCODE\n`0x0120681B`) to [Project Apicula](https://github.com/YosysHQ/apicula)** — the\ncommunity Gowin FPGA RE toolchain behind `yosys` + `nextpnr-himbaechel`.\n\nApicula 0.32 ships chipdbs for 10 Gowin devices; the GW1N-2 isn't one of them. This\nrepo builds the missing chipdb — through differential fuzzing of Gowin's own EDA\ntool plus parsing its shipped fabric/timing data — so the open flow can *unpack*\n(and eventually *author*) GW1N-2 bitstreams.\n\n\u003e ⚠️ **Status: work-in-progress research, not yet a usable tool.** The headline\n\u003e `gowin_unpack -d GW1N-2 …` workflow does not run for anyone until the chipdb is\n\u003e built and merged upstream. See [What you can do today](#what-you-can-do-today).\n\n\u003e This work began as a side quest of an open-firmware project for the FNIRSI 2C53T\n\u003e oscilloscope (whose FPGA is a GW1N-2). That backstory — and how it relates to that\n\u003e scope — lives in [`docs/09-openscope-context.md`](docs/09-openscope-context.md);\n\u003e it isn't needed to understand or contribute to the chipdb work.\n\n## Why GW1N-2 specifically is the wall\n\nApicula 0.32 (latest on PyPI) ships chipdbs for exactly these 10 devices:\n\n```\nGW1N-1, GW1N-4, GW1N-9, GW1N-9C, GW1NS-4, GW1NZ-1,\nGW2A-18, GW2A-18C, GW5A-25A, GW5AST-138C\n```\n\nNo GW1N-2. The IDCODE gate is a literal byte-match list in `apycula/bslib.py`\n(`read_bitstream`, ~lines 96–127); a GW1N-2 stream's device-ID command\n`06 00 00 00 01 20 68 1b` (= IDCODE `0x0120681B`) matches nothing and raises\n`ValueError(\"Unsupported device\")`. That check runs on the IDCODE *embedded in the\nbitstream*, **before** any `-d DEVICE` flag's database loads — so no flag works\naround it. The fix is a real GW1N-2 chipdb, not a config tweak.\n\n**Closest existing relative:** `GW1NZ-1`, IDCODE `0x0100681B` — shares the `…681B`\nfamily tail, differs in one byte. It's the natural template to fork from.\n\n## The method, in one paragraph\n\nIt's **differential fuzzing**, not random guessing. You use Gowin's own (free,\nclosed) EDA tool as a compile *oracle*: emit a minimal design that sets exactly one\nfabric feature (one LUT truth table, one routed wire, one IO buffer), compile it,\nemit a near-identical design differing only in that feature, compile that too, and\n**diff the two bitstreams** — the bits that flipped are the bits that control that\nfeature. Repeat systematically over the whole tile grid to build the\nbit ↔ feature map (the \"chipdb\"). Apicula *also* parses Gowin's shipped internal\nfabric/timing files (`.fse` / `.dat` / `.tm`), which already encode much of the\nstructure — so it's part vendor-file RE, part diff-fuzzing to confirm bit\npositions. Bottom-up order: grid/IO → LUT/DFF → routing → BRAM → PLL.\n\nYou do **not** need a real-world GW1N-2 bitstream to do any of this — device support\nis built entirely from fresh, tiny bitstreams generated and diffed on the fly. A\nreal-world stream is only useful as a final *validation target*: the first thing\nto `gowin_unpack` once the chipdb exists. (The one used here is gitignored, not\nredistributed — see [`reference/NOTES.md`](reference/NOTES.md).)\n\n## Status\n\n- [x] Confirmed the blocker (GW1N-2 absent from Apicula device DB)\n- [x] Extracted + verified a real-world validation bitstream (`reference/`, sha256 `5a0e7338…`)\n- [ ] Environment set up (Gowin EDA + Apicula clone + reference build) — `docs/01`\n- [ ] GW1NZ-1 reference build reproduced as a template — `docs/01`\n- [ ] GW1N-2 grid/IO mapped — `docs/02`\n- [ ] GW1N-2 logic primitives mapped (LUT/DFF) — `docs/02`\n- [ ] GW1N-2 routing mapped — `docs/02`\n- [ ] GW1N-2 BRAM/PLL mapped — `docs/02`\n- [ ] `gowin_unpack` succeeds on the validation bitstream\n- [ ] (stretch) nextpnr-himbaechel device data → author a custom GW1N-2 bitstream\n\n## What you can do today\n\nBe clear-eyed about the gate: **this is work-in-progress research, not yet a usable\ntool.** The headline `gowin_unpack -d GW1N-2 …` workflow does not run for anyone\nuntil the GW1N-2 chipdb exists and lands in Apicula (the unchecked boxes above).\nUntil then, here's the honest breakdown by audience:\n\n| You want to… | Status today |\n|---|---|\n| **Read the RE story** (how Gowin bitstreams work, how to fuzz a chipdb) | ✅ Ready now — start at `docs/00` |\n| **Reproduce the recon** (header/IDCODE parse, `bin2fs`, format checks) | ✅ Runnable now (Python; no Gowin EDA needed) |\n| **Run the fuzzing flow** (build the chipdb yourself) | ⚠️ Needs Gowin EDA + a Linux box — see `docs/01`, `docs/05` |\n| **Unpack a real GW1N-2 bitstream** | ⛔ Blocked on the chipdb (the milestone work above) |\n| **Modify FPGA behavior and re-pack** (experimental designs) | ⛔ Needs unpack **and** a working repack round-trip (`tools/roundtrip/`, early) |\n\n**Two unlock moments to watch for:** (1) the chipdb merging upstream into Apicula\nflips this from \"read along\" to \"anyone can unpack a GW1N-2 bitstream\"; (2) a\nworking unpack→modify→repack round-trip flips it to \"experimenters can modify a\nGW1N-2 bitstream\" — at which point this becomes an experimental sister repo for\ncustom GW1N-2 work (see [`docs/09`](docs/09-openscope-context.md)).\n\n## Reference value for other GW1N devices\n\nThe *bitstreams* this enables are device-locked — a Gowin bitstream carries its own\nIDCODE and a die-specific grid/frame layout, so a GW1N-2 image will not load on a\nGW1N-1, -4, or -9 (the IDCODE gate rejects it, and the fabric coordinates wouldn't\nline up even if forced). There's no \"author once, run across the family.\"\n\nWhat *does* transfer is the knowledge and the tooling. The GW1N family (the\n\"LittleBee\" generation) shares an architecture — the same LUT4/DFF primitives, IO\nblock structure, and routing-mux style — and Apicula is built around that, factoring\nshared per-die data rather than treating each device as a silo. (GW1N-2 here unpacks\nvia GW1N-1P5C die data: Gowin's own files already treat these as related dies.) So\nthe per-tile bit ↔ feature map and the fuzzing scripts (`tools/m*_*.py`) are a\nworked **reference implementation of the method**, reusable by anyone bringing\nanother not-yet-supported Gowin device into Apicula — not just the GW1N-2.\n\n## Honest scope\n\nTo be clear about what this is and isn't: the practical goal here is **not** a\nclean-sheet rework of the scope's FPGA design. The aim is the narrower, more\ntractable one — finding ways to *add features by modifying the existing stock\nbitstream*, ideally without fully reverse-engineering the original design. That work\nis inherently bound to a specific device and the scope's context.\n\nSo for anyone arriving without the 2C53T hardware and that context, this repo is\nbest read as a **research and reference resource** — a documented method, a chipdb,\nand a set of fuzzing tools — rather than a tool you can point at your own board and\nimmediately use. That's by design, and the cross-family notes above are exactly the\npart that travels.\n\n## Docs\n\n- `docs/00-background.md` — the device, the IDCODE wall, and how bitstream fuzzing works\n- `docs/01-environment-setup.md` — Gowin EDA, Apicula clone, reproduce a known-good device build\n- `docs/02-methodology.md` — the bottom-up fuzzing plan, using GW1NZ-1 as the template\n- `docs/03-workplan.md` — milestone checklist and how we'll know each step worked\n- `docs/04-contributing.md` — how to land GW1N-2 support upstream the way maintainers expect\n- `docs/05-needs-david.md` — the human-only blockers (Gowin EDA install, Linux env)\n- `docs/09-openscope-context.md` — origin story + relationship to the OpenScope firmware project\n- `setup.sh` — runnable env bootstrap for the Linux box (verified against the real repo)\n\n## License\n\nMIT (see [`LICENSE`](LICENSE)), matching Apicula's license so any chipdb produced\nhere can be **contributed upstream to Apicula** cleanly. This repo is workspace +\ntooling + notes, not a fork; the chipdb work lands in a clone of the Apicula repo\n(see `docs/01`).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdavidclawson%2Fgw1n2-apicula","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdavidclawson%2Fgw1n2-apicula","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdavidclawson%2Fgw1n2-apicula/lists"}