{"id":22085345,"url":"https://github.com/dawsonjon/chips_v","last_synced_at":"2025-10-29T22:42:04.442Z","repository":{"id":142498615,"uuid":"295802216","full_name":"dawsonjon/chips_v","owner":"dawsonjon","description":"RISC-V System on Chip Builder","archived":false,"fork":false,"pushed_at":"2020-09-27T16:29:29.000Z","size":1127,"stargazers_count":7,"open_issues_count":0,"forks_count":2,"subscribers_count":3,"default_branch":"master","last_synced_at":"2023-03-13T22:20:15.918Z","etag":null,"topics":["c","chip-builder","chips","embedded","fpga","fpga-soc","python","risc-v","riscv","soc","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/dawsonjon.png","metadata":{},"created_at":"2020-09-15T17:31:19.000Z","updated_at":"2022-08-30T20:47:44.000Z","dependencies_parsed_at":null,"dependency_job_id":"1d81965b-95ff-403a-b305-d9b4e098f45a","html_url":"https://github.com/dawsonjon/chips_v","commit_stats":null,"previous_names":[],"tags_count":null,"template":null,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dawsonjon%2Fchips_v","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dawsonjon%2Fchips_v/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dawsonjon%2Fchips_v/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dawsonjon%2Fchips_v/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/dawsonjon","download_url":"https://codeload.github.com/dawsonjon/chips_v/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":227463803,"owners_count":17778465,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["c","chip-builder","chips","embedded","fpga","fpga-soc","python","risc-v","riscv","soc","verilog"],"created_at":"2024-12-01T01:13:38.326Z","updated_at":"2025-10-29T22:42:04.362Z","avatar_url":"https://github.com/dawsonjon.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdawsonjon%2Fchips_v","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdawsonjon%2Fchips_v","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdawsonjon%2Fchips_v/lists"}