{"id":35279635,"url":"https://github.com/dbalsom/cga_sim","last_synced_at":"2026-04-02T00:24:39.675Z","repository":{"id":328558044,"uuid":"1115941928","full_name":"dbalsom/cga_sim","owner":"dbalsom","description":"A digital logic simulation of the IBM CGA card","archived":false,"fork":false,"pushed_at":"2025-12-14T00:44:04.000Z","size":231,"stargazers_count":17,"open_issues_count":0,"forks_count":1,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-01-03T03:26:45.478Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/dbalsom.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-12-13T21:39:15.000Z","updated_at":"2025-12-16T20:52:22.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/dbalsom/cga_sim","commit_stats":null,"previous_names":["dbalsom/cga_sim"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/dbalsom/cga_sim","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dbalsom%2Fcga_sim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dbalsom%2Fcga_sim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dbalsom%2Fcga_sim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dbalsom%2Fcga_sim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/dbalsom","download_url":"https://codeload.github.com/dbalsom/cga_sim/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dbalsom%2Fcga_sim/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28397826,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-13T14:36:09.778Z","status":"ssl_error","status_checked_at":"2026-01-13T14:35:19.697Z","response_time":56,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-12-30T14:22:04.839Z","updated_at":"2026-04-02T00:24:39.661Z","avatar_url":"https://github.com/dbalsom.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# simcga\n\nThis is a digital logic simulation of the IBM CGA card, for the excellent [Digital](https://github.com/hneemann/Digital) digital logic simulator by Helmut Neemann. \n\n\u003cimg src=\"./img/screenshot_01.png\" width=\"800\" /\u003e\n\n# Why?\n\nI wanted to study the CGA card to better understand its operation and the operation of undefined mode flag combinations. It was also a good exercise to learn Verilog.\n\n# Limitations\n\n - The CPU-side interface is not implemented. You have to manually load data into VRAM and toggle the bits you want in the mode control and color control registers.\n - The simulation comes with the splash screen for the incredible PC demo [Area 5150](https://www.pouet.net/prod.php?which=91938) loaded into VRAM and light blue in the CC register like the demo sets it.\n\n# Important Note\n\nDigital has a \"VGA\" output component, although the built-in timings are not compatible with CGA so I had to patch Digital to add support for CGA.\nYou can find the relevant changes in this branch of my fork of Digital [here](https://github.com/dbalsom/Digital_videomod/tree/cga-video-modes).\n\nPlease don't ask me how to build it. I've never built Digital, I just patched the JAR. The fork is provided for GPL3 compliance. \n\n# How to Use\n\n## Portable Windows Install \n\nHead over to [releases](https://github.com/dbalsom/cga_sim/releases) and grab one of the portable install builds for Windows. It bundles OpenJDK, Icarus Verilog and Digital for you -- just run `run_cga_sim.bat`.\n\n## Installing Manually\n\n### Install Prerequisites\n\n - Java of some sort. I'd recommend OpenJDK. There's a million ways to install this, so I will trust you can Google the best way for your platform.\n - Install or build [Icarus Verilog](https://github.com/steveicarus/iverilog) on your system.\n - Install the [v0.31 release of Digital](https://github.com/hneemann/Digital/releases/tag/v0.31). Download the `Digital.jar` file included in the [release zip](https://github.com/dbalsom/cga_sim/releases/tag/v0.1) and copy it over the `Digital.jar` in the installation.\n\n - Run Digital, and go to Edit -\u003e Settings. \n   - Click on the Advanced tab.\n   - Click on the browse button (...) by the `IVerilog` text box, and locate the `iverilog` binary, wherever you installed it.\n\n### Running the simulation\n  - The main simulation file will be named `cga_NN.dig` where NN is the current version. Open it via File -\u003e Open.\n  - Press the play button in the toolbar to start the simulation. It may take a minute for the simulation to produce a frame. \n    - A window will pop up when the simulator has acquired sync lock on the output signal. You may need to resize this window to see the entire output. \n\n  - The CRTC is initialized for Area 5150's \"ANSI from hell\" mode to show the demo's splash screen. There are few mode presets in the `mc6845_10.v` file you can edit if you say, want regula r 80x25 text mode. Just edit the `STARTUP_MODE` variable at the top of the file and save.  Digital should pick up the changes the next time you start the simulation.\n\n  - You can load video memory with different things. \n    - Locate the MCM4517 component in the \"Video Memory\" box at bottom-center. \n    - Right click on the MCM4517 and click *open*.\n    - Right click on the 'EEPROM' component and click *Edit*.\n    - Go to File, Load, and select a new VRAM dump. The file should be a 16KB binary. Note: CGA VRAM organization may not be what you expect - odd bytes from the CPU perspective are offset by 4096. \n      - You can format linear dumps of CGA VRAM to the CGA's internal format using the provided [cga_swizzle](./vram/cga_swizzle.py) script.\n      - Some ready-made VRAM images are supplied in [vram](vram/).\n\nNote that if you want to change the overscan color you will need to set a new color in the Color Control register directly to the right of the CRTC. \nThere is a CGA palette reference at the top of the diagram. \n\n# Special Thanks\n\n- *Helmut Neemann* of course for making the kickass [Digital](https://github.com/hneemann) simulator.\n- *Stephen Williams* for making [Icarus Verilog](https://github.com/steveicarus/iverilog).\n- *hkz* for redrawing all the [CGA schematics in KiCad](https://github.com/hkzlab/CGA_Schematics) which was very helpful.\n- *Trixter*, *reenigne*, *VilerR*, *PCRetroTech* and the rest of the crew\n- *John Elliott* for his excellent [CGA Notes](https://www.seasip.info/VintagePC/cga.html)\n\n# Licenses\n\n[Digital](https://github.com/hneemann/Digital) is licensed under the GPL3 license.\nSource for all modifications is available [here](https://github.com/dbalsom/Digital_videomod/tree/cga-video-modes).\n\n[Icarus Verilog](https://github.com/steveicarus/iverilog) is licensed under the GPL2 license.","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdbalsom%2Fcga_sim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdbalsom%2Fcga_sim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdbalsom%2Fcga_sim/lists"}