{"id":20081772,"url":"https://github.com/delhatch/mandel_hls","last_synced_at":"2026-03-05T07:02:36.714Z","repository":{"id":203001971,"uuid":"118304145","full_name":"delhatch/Mandel_HLS","owner":"delhatch","description":"Using Vivado HLS to create floating point IP, used to accelerate a Zynq system. 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This Xilinx tool creates HDL from C code.\n\nI also wanted to explore passing, processing and receiving floating point values. My default number system is fractional integers, so I wanted to see how performance is impacted by processing floats.\n\nThe result is that Vivado HLS did a good job in creating IP with a small footprint. The problem (a speed problem) comes from the resulting large number of cycles (3 or 4 cycles at 100 MHz) required to do a fp multiply.\n\nI would normally write Verilog HDL directly instead using a higher-level language. But using the HLS tool did allow me to create floating point IP very quickly and easily.\n\n** Memory-mapped VGA display\n\nThe project uses the memory-mapped VGA display I used in other projects. See those for more details. \n\n** Performance\n\nAs you can see, the sythesized floating point engine requires 24 cycles for each loop. In comparison, the fixed-point implementation I wrote (see the Zedboard_Mandel project) requires just 4 cycles per loop. Quite a penalty for floating point, and perhaps for using C code to generate the IP as well.\n\n![screenshot](https://github.com/delhatch/Mandel_HLS/blob/master/cycles.JPG)\n\nTherefore, even with 8 engines, the Mandelbrot image takes 1.4 seconds to create. This is better than the pure-ARM version that required 2.2 seconds to compute a frame, but this was not as much improvement as I expected.\n\nThe integer version, written in Verilog, and writing directly to the VGA frame buffer (no ARM processor involved) was able to achieve 18.6 frames per second.\n\n** Improvements\n\nThis project is mainly a demonstration of how to use Vivado HLS to create IP, and it was successful in that regard.\n\nOne area for focus would be to try to speed up the floating-point engine, but this might not be possible given how many cycles floating-point calculations require.\n\nHowever, even with the relatively slow engines compared to fixed-point engines, the Zynq processor's C code is the bottleneck. The engines need to be able to access the VGA frame buffer directly, as seen in the Zedboard_Mandel project.\n\n\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdelhatch%2Fmandel_hls","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdelhatch%2Fmandel_hls","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdelhatch%2Fmandel_hls/lists"}