{"id":17275414,"url":"https://github.com/devbisme/myhdl-resources","last_synced_at":"2025-04-12T19:35:30.732Z","repository":{"id":54087555,"uuid":"109852216","full_name":"devbisme/myhdl-resources","owner":"devbisme","description":"A collection of awesome MyHDL tutorials, projects and third-party tools.","archived":false,"fork":false,"pushed_at":"2021-07-07T19:54:45.000Z","size":386,"stargazers_count":93,"open_issues_count":0,"forks_count":17,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-03-26T13:52:30.413Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/devbisme.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"contributing.md","funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2017-11-07T15:15:26.000Z","updated_at":"2024-10-25T12:47:42.000Z","dependencies_parsed_at":"2022-08-13T06:40:19.419Z","dependency_job_id":null,"html_url":"https://github.com/devbisme/myhdl-resources","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/devbisme%2Fmyhdl-resources","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/devbisme%2Fmyhdl-resources/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/devbisme%2Fmyhdl-resources/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/devbisme%2Fmyhdl-resources/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/devbisme","download_url":"https://codeload.github.com/devbisme/myhdl-resources/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248622755,"owners_count":21135104,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-15T08:56:11.686Z","updated_at":"2025-04-12T19:35:30.709Z","avatar_url":"https://github.com/devbisme.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# MyHDL Resources\n\n\u003e A curated list of tutorials, projects, and third-party tools to be used in conjunction with the\nopen source [MyHDL](http://myhdl.org/) hardware design language.\n\n*You can add your own stuff to this! Please read the [contribution guidelines](contributing.md) to see how.*\n\n\n\n## Table of Contents\n\n\u003c!-- TOC depthFrom:2 depthTo:6 withLinks:1 updateOnSave:1 orderedList:0 --\u003e\n\n- [MyHDL Resources](#myhdl-resources)\n  - [Table of Contents](#table-of-contents)\n  - [Tutorials](#tutorials)\n  - [Projects](#projects)\n  - [Third-Party Tools](#third-party-tools)\n  - [License](#license)\n\n\u003c!-- /TOC --\u003e\n\n\n## Tutorials\n\n- [MyHDL Reference Manual](http://docs.myhdl.org/en/stable/) -\nThe go-to document for the MyHDL language.\n\n- [Hello World](http://myhdl.org/docs/examples/helloworld.html) -\nShows how a demonstrator design that was originally coded in VHDL can be done in MyHDL.\n\n- [Flip-Flops and Latches](http://myhdl.org/docs/examples/flipflops.html) -\nExplains basic MyHDL usage with small, widely-known circuits.\n\n- [Bitonic Sort](http://myhdl.org/docs/examples/bitonic/) -\nPresents possibilities for describing hardware structures in MyHDL, focusing on\na classic sorting function.\n\n- [PygMyHDL Tutorials](https://github.com/devbisme/pygmyhdl#getting-started) -\nA sequence of Jupyter notebooks that use PygMyHDL (MyHDL + simple wrapper)\nto describe, compile, download and run several digital logic circuits on the\nlow-cost iCEstick FPGA board.\n\n- [MyHDL Cheat Sheet](https://bitbucket.org/nico-dev/myhdl_cheat_sheet/src) -\nAn abstract for the MyHDL language keywords.\n\n- [modbv Example](https://bitbucket.org/cfelton/examples/src/tip/rrs_modbv/) - \nAn example of the use of the modbv type introduced in MyHDL 0.8.\n\n- [LED Strober](https://www.fpgarelated.com/showarticle/25.php) - \nShows a complete implementation of a circuit that recreates\nthe strobe effect of the Knightrider Trans Am.\n\n- [Audio Echo](https://www.fpgarelated.com/showarticle/34.php) -\nDescribes how to produce an echo on a stream of digitized audio samples.\nA [companion article](https://www.fpgarelated.com/showarticle/41.php) adds further details\nconcerning the actual implementation with an AIC23 codec chip.\n\n- [Simple Co-Simulation Example](https://gist.github.com/j-marjanovic/1cd36b9da44280e890b6) -\nThis code snippet uses three modules to present the absolute minimum for a\nco-simulation of Verilog code and MyHDL code.\n\n- [OO Design in MyHDL](https://gist.github.com/josyb/2e43c9ad7ffa772d52dfd66cb660dc4a) -\nAn example of using object-oriented design principles with MyHDL.\n\n- [FPGA Designs With MyHDL](http://fpga-designs-with-myhdl.readthedocs.io/en/latest/index.html) -\nA reimagining of [these VHDL/Verilog designs](http://pythondsp.readthedocs.io/en/latest/pythondsp/toc.html#fpga-designs-with-verilog-and-systemverilog) in MyHDL.\n\n\n## Projects\n\n- [Johnson Counter](http://myhdl.org/docs/examples/jc2.html) -\nPresents the design of a reversible, glitch-free, 4 bit Johnson counter.\n\n- [Stopwatch](http://myhdl.org/docs/examples/stopwatch/) -\nDescribes the design of a simple stopwatch.\n\n- [Pulse Width Modlator](https://bitbucket.org/cfelton/examples/src/tip/pwm?at=default) -\nA simple PWM along with several test setups.\n\n- [Cordic-Based Sine Computer](http://myhdl.org/docs/examples/sinecomp/) -\nPresents the design of a sine and cosine computer.\n\n- [Hardware Sorters](https://github.com/devbisme/Hardware-Sorters) -\nA [Jupyter](jupyter.org) notebook describing, simulating, and comparing \ntwo hardware-based circuits for sorting a list of numbers.\n\n- [Exploring Random Number Generators with MyHDL](https://github.com/devbisme/CAT-Board/blob/master/tests/RNG_with_MyHDL.ipynb) -\nIllustrates the advantages of using MyHDL and Python in designing and testing a random number generator (RNG).\n\n- [Simple IIR Filter](https://bitbucket.org/cfelton/examples/src/tip/siir/) -\nA simple infinite impulse response (IIR) Lowpass Direct Form I Filter.\n\n- [Simple FIR Filter](https://bitbucket.org/cfelton/examples/src/tip/firfilt?at=default) -\nA simple finite impulse response (FIR) filter.\n\n- [Recursive FFT](https://bitbucket.org/cfelton/examples/src/tip/rfft/) -\nFast Fourier Transform in MyHDL and translatable to Verilog or VHDL for hardware implementation.\nSee [this](https://www.dsprelated.com/showcode/16.php) for additional explanation.\n\n- [AIC23b Audio Codec Interface](https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23?at=default) -\nAn interface for configuring the [AIC23 codec](http://www.ti.com/product/TLV320AIC23B) and sampling/generating audio signals.\n\n- [myhdl_lib](https://github.com/nkavaldj/myhdl_lib) -\nA MyHDL library of generic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc. All components are tested with Icarus Verilog simulator.\n\n- [rhea](https://github.com/cfelton/rhea) -\nA collection of HDL cores along with a small set of utilities to augment the MyHDL types and functions as well as FPGA build automation tools.\n\n- [KalmanFilter](https://github.com/josyb/KalmanFilter) - \nA simple, low-resource usage Kalman Filter using shared resources.\n\n- [myhdl_simple_uart](https://github.com/andrecp/myhdl_simple_uart) - \nImplements a simple UART in MyHDL and generates the VHDL files. It has been tested in a DE2-115 board.\n\n- [Spiking Neuron](https://github.com/CodeReclaimers/myhdl-experiments/blob/master/izhikevitch/neuron.py) -\nImplements a spiking neuron based on the model described in\nIzhikevich, E. M., \"Simple Model of Spiking Neurons\"\nIEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 6, NOVEMBER 2003.\n\n- [Algol RISCV CPU core](https://github.com/AngelTerrones/Algol) -\nA CPU core that implements the RISC-V RV32IM Instruction Set.\n\n- [alt.hdl](https://github.com/cfelton/alt.hdl) -\nA collection of complete and partial design examples built using MyHDL, bsv, and chisel.\n\n- [PyMIPS](https://github.com/mgaitan/pymips) -\nA formal implementation of a MIPS processor as described in *Computer Organization and Design* by Hennessy/Patterson.\n\n- [RISC-V](https://github.com/jck/riscv) -\nA RISC-V implementation and tools.\n\n- [MyBlaze](https://github.com/wware/myblaze) -\na synthesizable clone of the MicroBlaze Soft Processor.\n\n- [Skip-Gram Model for Word Embeddings](https://github.com/gw0/rs-skip-gram-in-myhdl) -\nImplementation in MyHDL of a neural network using the skip-gram model for natural language processing.\n\n- [VGA Bouncing Ball](https://github.com/on1arf/myhdl-vga_bounceball) -\nA circuit that displays a bouncing ball on a VGA monitor.\n\n- [Whitebox](https://github.com/testaco/whitebox) -\nA cross between a smartphone and a software defined radio with the DSP section described using MyHDL.\n\n- [HDL-deflate](https://github.com/tomtor/HDL-deflate) -\nImplementation of deflate (de)compress RFC 1950/1951.\n\n- [Kea](https://github.com/SmartAcoustics/Kea) -\nSome useful HDL blocks, mainly an AXI Lite register subsystem, along with supporting AXI Lite and Stream interfaces and associated BFMs.\n\n- [Verilog PCIexpressComponents](https://github.com/mongrelgem/Verilog-PCIexpress-Components) -\nA collection of PCI express related components including a full MyHDL \u0026 Verilog testbench with intelligent bus cosimulation endpoints.\n\n- [myBFSK](https://github.com/Hypotalamus/myBFSK) -\nExample of receiver for continuous phase binary frequency shift keying signals with modulation index less then 1.0 written in myHDL.\n\n- [CS3339-MIPS32](https://github.com/grantslape/CS3339-MIPS32) -\nThis project simulates a MIPS-like 5 stage pipeline through co-simulation between Python and Icarus Verilog. The machine is implemented with a 32-bit architecture through the myHDL library.\n\n- [1pCPU](https://github.com/pcornier/1pCPU) -\nA small 8bit CPU written with MyHDL in a Jupyter notebook.\n\n- [jupyosys](https://hackaday.io/project/171216-jupyosys) -\nMyHDL extensions to support direct RTL generation and synthesis through yosys \n\n## Third-Party Tools\n\n- [myhdlpeek](https://github.com/devbisme/myhdlpeek) - \nA Python package that lets you monitor and display signal waveforms from your MyHDL digital design in a Jupyter notebook.\n\n- [PygMyHDL](https://github.com/devbisme/pygmyhdl) - \nA Python package that places a thin-wrapper around MyHDL to make it a bit easier for\nbeginners to get started.\n\n- [Ovenbird](https://github.com/hgomersall/Ovenbird) - \nA tool for merging the MyHDL workflow with Vivado.\n\n- [MyHDLXilinxUnisimLib](https://bitbucket.org/nico-dev/myhdl_xilinx_unisim_lib/) - \nMyHldXilinxUnisimLib lets you use Xilinx Unisim components within a MyHDL project.\n\n- [Synthia](https://github.com/nturley/synthia) -\nA simple IDE that uses MyHDL, yosys, and arachne-pnr to target the ICEStick.\n\n- [pyFDA](https://github.com/chipmuenk/pyFDA) -\nA GUI-based tool for analysing and designing discrete time filters.\nMay be using MyHDL to generate HDL implementations of the filters.\n\n- [Veriutils](https://github.com/hgomersall/Veriutils) -\nA collection of utilities for verification of HDL designs created using MyHDL.\n\n- [MyHDL Numeric](https://github.com/jmgc/myhdl-numeric) -\nMyHDL-numeric is an enhancement of the MyHDL package which provides support for multiple VHDL entities (MEP110) and fixed-point numbers (MEP111).\n\n- [myhdl2dot](https://github.com/harboleas/myhdl2dot) -\nGenerates a flowgraph for a MyHDL design using graphviz.\n\n- [VSCode MyHDLTools](https://github.com/rbnprdy/vscode-myhdltools) -\nProvides some helpful code generators for using MyHDL for Verilog Cosimulation.\n\n- [HDL playground](https://github.com/hackfin/hdlplayground) -\nJupyter notebook environment for MyHDL/VHDL/Verilog synthesis from the Browser, based on the jupyosys project (Docker container or Google Binder)\n\n\n## License\n\n[![CC0](http://mirrors.creativecommons.org/presskit/buttons/88x31/svg/cc-zero.svg)](https://creativecommons.org/publicdomain/zero/1.0/)\n\nTo the extent possible under law, [Dave Vandenbout](devb@xess.com) has waived all copyright and related or neighboring rights to this work.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdevbisme%2Fmyhdl-resources","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdevbisme%2Fmyhdl-resources","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdevbisme%2Fmyhdl-resources/lists"}