{"id":26227611,"url":"https://github.com/dho-rae/computer-architecture","last_synced_at":"2026-04-20T23:32:32.821Z","repository":{"id":280196684,"uuid":"941263139","full_name":"dho-rae/Computer-Architecture","owner":"dho-rae","description":"This repository contains three interconnected projects exploring fundamental computer architecture concepts. The projects focus on assembly language programming, memory management, and CPU simulation. The work was completed as part of a graduate-level Computer Architecture course.","archived":false,"fork":false,"pushed_at":"2025-03-10T00:24:49.000Z","size":12,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-10T01:32:28.884Z","etag":null,"topics":["assembly","computer-architecture","cpu-simulation","memory-management","university-project"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/dho-rae.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-03-01T21:45:40.000Z","updated_at":"2025-03-10T00:26:12.000Z","dependencies_parsed_at":null,"dependency_job_id":"1968de84-2f18-4ec6-a483-fb17a21ba125","html_url":"https://github.com/dho-rae/Computer-Architecture","commit_stats":null,"previous_names":["dho-rae/computer-architecture"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dho-rae%2FComputer-Architecture","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dho-rae%2FComputer-Architecture/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dho-rae%2FComputer-Architecture/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dho-rae%2FComputer-Architecture/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/dho-rae","download_url":"https://codeload.github.com/dho-rae/Computer-Architecture/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243285620,"owners_count":20266849,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembly","computer-architecture","cpu-simulation","memory-management","university-project"],"created_at":"2025-03-12T20:18:06.693Z","updated_at":"2025-12-28T03:18:01.672Z","avatar_url":"https://github.com/dho-rae.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Computer-Architecture\n\n## Overview\nThis repository contains coursework projects that focus on understanding the fundamentals of CPU architecture, instruction decoding, caching mechanisms, and pipeline simulation.\n\n## Projects\n\n### 1) Instruction Decoder\n- Extracts specific bits from 32-bit MIPS instructions.\n- Supports both R-format and I-format instructions.\n- Demonstrates instruction decoding using bit masking and shifting.\n\n**Folder**: [`Project-1`](./Project-1)  \n**Main file**: [`instruction_decoder.py`](./Project-1/instruction_decoder.py)  \n\n### 2) Cache Simulator\n- Simulates a direct-mapped cache with 16 slots.\n- Implements cache read, write, and display operations.\n- Uses write-back policy to update main memory.\n\n**Folder**: [`Project-2`](./Project-2)  \n**Main file**: [`cache.py`](./Project-2/cache.py)  \n\n### 3) Pipeline Simulation\n- Simulates a five-stage instruction pipeline (IF, ID, EX, MEM, WB).\n- Implements register forwarding and hazard detection.\n- Displays all pipeline register states at each clock cycle.\n\n**Folder**: [`Project-3`](./Project-3)  \n**Main file**: [`pipeline_simulator.py`](./Project-3/pipeline_simulator.py)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdho-rae%2Fcomputer-architecture","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdho-rae%2Fcomputer-architecture","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdho-rae%2Fcomputer-architecture/lists"}