{"id":23586515,"url":"https://github.com/doctorwkt/mmu09","last_synced_at":"2025-07-31T21:05:05.665Z","repository":{"id":191946430,"uuid":"683624252","full_name":"DoctorWkt/MMU09","owner":"DoctorWkt","description":"A 6809 single-board computer with an MMU","archived":false,"fork":false,"pushed_at":"2023-12-08T23:23:21.000Z","size":10094,"stargazers_count":13,"open_issues_count":0,"forks_count":0,"subscribers_count":4,"default_branch":"master","last_synced_at":"2025-03-31T07:51:15.342Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/DoctorWkt.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2023-08-27T07:05:22.000Z","updated_at":"2024-12-07T09:18:53.000Z","dependencies_parsed_at":"2023-12-09T01:03:35.274Z","dependency_job_id":null,"html_url":"https://github.com/DoctorWkt/MMU09","commit_stats":null,"previous_names":["doctorwkt/mmu09"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DoctorWkt%2FMMU09","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DoctorWkt%2FMMU09/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DoctorWkt%2FMMU09/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DoctorWkt%2FMMU09/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/DoctorWkt","download_url":"https://codeload.github.com/DoctorWkt/MMU09/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":252838966,"owners_count":21812083,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-27T04:11:28.233Z","updated_at":"2025-05-07T07:47:09.524Z","avatar_url":"https://github.com/DoctorWkt.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# MMU09 - A 6809 single-board computer with an MMU\n\nI'm working on a 6809 single-board computer with an external MMU, so I can\nbring up a Unix-like operating system for it. Currently this is the `xv6`\nfilesystem with process code partially borrowed from `xv6`. The library \ncomes from FUZIX and the userland comes from multiple places, some\nself-written.\n\nThe [Hardware](Hardware) folder has the hardware version of the system.\nThe main components are: the 6809, 32K ROM, 512K RAM, a dual UART, a\nCH375 device for storage and an ATF1508 CPLD to implement address decoding\nand the MMU.\n\nThe [Docs](Docs) folder has details of the design and the implementation.\n\nThe [Verilog](Verilog) folder has the Verilog code for the CPLD as well as\na Verilog implementation of the 6809, ROM, RAM and a UART. This allows me to\ntest the MMU to ensure that it will work before I build the hardware.\n\nI'd really like to get some feedback, ideas etc. on this project.\n\n## Status - 1st September 2023\n\nI've updated the schematic with the pin headers to make the PCB into a \"hat\"\nwhich will sit on top of an Atmega 2560. I'll be able to use this to monitor\nand partially control the SBC.\n\nI've made a first attempt at laying out the components on a PCB, and there\nis an archive of the Kicad project in the [Hardware](Hardware) folder.\n\nIn the [Verilog](Verilog) folder, there is now an Icarus Verilog simulation of the\nsystem. I can run 6809 instructions and see the system go in/out of kernel\nmode, and see the page mappings change.\n\nThe CPLD Verilog code now has reset functionality.\n\n## Status - 10th September 2023\n\nI now have a completed PCB design; see the [Hardware](Hardware) folder for a schematic\nand views of the PC board.\n\n## Status - 18th September 2023\n\nI have ported the xv6 filesystem code from [https://github.com/DoctorWkt/Nine-E/](https://github.com/DoctorWkt/Nine-E/).\nThis gives me a Unix-like environment but with only one program running at a time.\nI've used the address decoding on the MMU09 to give each program 63.5K of address\nspace. This works in the Salmi simulator.\n\nI've ordered the PCB and the parts to build the hardware; they haven't arrived yet, sigh.\n\n## Status - 4th October 2023\n\nI've built the board and, with the exception of the DS12C887, everything\nworks at 14.75MHz. I've changed the CPLD code to have a stack of four\nprevious user/kernel modes; this allows us to go from user mode to kernel\nmode, followed by two nested interrupts, and return safely back to user mode.\n\nProgramming the CPLD with the Verilog -\u003e Yosys -\u003e JED workflow is nice and\neasy, using the workflow from [https://github.com/hoglet67/atf15xx_yosys](https://github.com/hoglet67/atf15xx_yosys).\nI'm then using the `jed2svf` converter from\n[https://whitequark.github.io/prjbureau/tools/fuseconv.html](https://whitequark.github.io/prjbureau/tools/fuseconv.html) to make the\nSVF file, and a FT232H device and OpenOCD to send the SVF file to the ATF1508 CPLD,\nbased on the information from\n[https://www.hackup.net/2020/01/erasing-and-programming-the-atf1504-cpld/](https://www.hackup.net/2020/01/erasing-and-programming-the-atf1504-cpld/).\n\nI have a simple monitor which allows me to dump memory contents,\nalter memory and run a program in user mode. There are syscalls to read from\n\u0026 write to the UART, and to exit back to the monitor.\n\n## Status - 17th October 2023\n\nAfter fighting a problem with RAM for over a week, I found that my Verilog code\nfor the RAM chip select was wrong. Now fixed. This allows me to get the xv6\nfilesystem code up and running on the board. Each program now has a usable address\nspace of $0000 to $FDFF, with the constraint that only code can be in $0000 to $1FFF.\n\n## Status - December 2023\n\nThings have been rearranged. I now have processes and multitasking, but\nno pre-emption as yet. There is `fork()`, `exec()`, `exit()` and `wait()`\nalong with `pipe()`.\n\nI got the wiring of the RTC wrong, but I should be able to use the CPLD\nto generate clock ticks and do time keeping and pre-emption this way.\n\nI need to rewrite the shell to do file redirection in the child, not in the\nparent process. The shell worked when there was only one process; this is\nno longer the case.\n\nProcesses now have 63.5K of address space with the constraint that the lower\n8K of address space cannot contain any data.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdoctorwkt%2Fmmu09","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdoctorwkt%2Fmmu09","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdoctorwkt%2Fmmu09/lists"}