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Reelay implements state-of-the-art [runtime verification](https://en.wikipedia.org/wiki/Runtime_verification) techniques to construct runtime monitors that check temporal behaviors of the system against system-level requirements. Hence, Reelay can be used to enhance rigorous systems engineering practices by formalizing and automating the assessment phase.\n\n## Main Features\n\n- Formal specification of temporal properties\n- Provably correct monitor construction from the specification\n- Fast and frugal runtime requirement checking (very low overhead)\n- Simple but non-restrictive user interface\n- Available for C++ and Python\n\n## Rye Format\n\nReelay reads executable specifications written in plain text and verifies that the system does what those specifications say at runtime. In order to construct runtime monitors automatically, those specifications must follow some basic syntax rules, called Reelay Expression (Rye) format. See the reference for the [Rye format](docs/rye.md) for more details.\n\n## Get Started\n\nThe next steps for you are to install Reelay [from source](docs/install.md) and follow through [the tutorial](docs/gs_intro.md) to learn how to use Reelay monitors from [C++](docs/gs_cpp.md) and [Python](docs/gs_python.md). Check out [the documentation](https://doganulus.github.io/reelay/) for more details.\n\n## Contribute\n\nCurrently Reelay does not have a contribution guideline. However, we always welcome bug reports, enhancements, and comments regarding the project. Please use the [Issues](https://github.com/doganulus/reelay/issues) page if you have a bug report, enhancement, or comment.\n\n## Cite\n\nIf you are using Reelay in an academic work, please cite\n\n- [Online monitoring of metric temporal logic using sequential networks](https://arxiv.org/abs/1901.00175)\n\nwhere the main technique has been explained throughtly. Further bits of techniques and motivations can be traced in the following papers.\n\n- [First-order temporal logic monitoring with BDDs](https://link.springer.com/article/10.1007/s10703-018-00327-4)\n- [Sequential circuits from regular expressions revisited](https://arxiv.org/abs/1801.08979)\n\nPlease also look at the [performance notes](docs/performance.md) if you compare the performance between tools.\n","funding_links":["https://github.com/sponsors/doganulus"],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdoganulus%2Freelay","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdoganulus%2Freelay","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdoganulus%2Freelay/lists"}