{"id":25067627,"url":"https://github.com/dopebiscuit/ieee-digital-ic-design","last_synced_at":"2026-02-16T14:01:48.945Z","repository":{"id":190926474,"uuid":"683606124","full_name":"DopeBiscuit/IEEE-Digital-IC-Design","owner":"DopeBiscuit","description":"This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.","archived":false,"fork":false,"pushed_at":"2023-10-10T15:01:19.000Z","size":12022,"stargazers_count":4,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-09-12T13:58:07.756Z","etag":null,"topics":["digital-design-and-computer-organization","logic-design","verilog-project"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/DopeBiscuit.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-08-27T05:47:54.000Z","updated_at":"2025-04-10T16:11:50.000Z","dependencies_parsed_at":"2025-03-31T14:49:46.247Z","dependency_job_id":"5a9ca9c5-56ca-4b8f-833f-03a75e3bf69f","html_url":"https://github.com/DopeBiscuit/IEEE-Digital-IC-Design","commit_stats":null,"previous_names":["dopebiscuit/ieee-digital-ic-design"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/DopeBiscuit/IEEE-Digital-IC-Design","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DopeBiscuit%2FIEEE-Digital-IC-Design","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DopeBiscuit%2FIEEE-Digital-IC-Design/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DopeBiscuit%2FIEEE-Digital-IC-Design/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DopeBiscuit%2FIEEE-Digital-IC-Design/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/DopeBiscuit","download_url":"https://codeload.github.com/DopeBiscuit/IEEE-Digital-IC-Design/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DopeBiscuit%2FIEEE-Digital-IC-Design/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29509253,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-16T09:05:14.864Z","status":"ssl_error","status_checked_at":"2026-02-16T08:55:59.364Z","response_time":115,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["digital-design-and-computer-organization","logic-design","verilog-project"],"created_at":"2025-02-06T20:58:08.821Z","updated_at":"2026-02-16T14:01:48.929Z","avatar_url":"https://github.com/DopeBiscuit.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003cdiv align=\"center\"\u003e\u003cimg src=\"https://i.imgur.com/Ba9CDl0.jpg\" alt=\"IEEE ASUSB logo\" width=\"300\" height=\"300\"/\u003e\u003c/div\u003e\n\n# IEEE-Digital-IC-Design\n**This repo is for my IEEE Digital IC Design workshop, an introduction to digital design using verilog, and this is a documentation of my tasks, all folders include pdf with the task's requirements.**\n\n\n## Lecture 1 - Intro to:\n-  Introduction to verilog and it's concurrent behaviour.\n-  Syntax, logical operators, arithmetic operators and modules.\n-  Gate-level design.\n-  Structural design.\n\n## Task 1: \n- **Basic Logic circuits using Gate-level and Structural design**\n\u003chr\u003e\n\n## Lecture 2 - Intro to: \n- Sequential blocks (always, initial), how to use them, what is the senstivity list.\n- Behavioural desgin.\n- Testbench files\n- .do file / scripting.\n- Basic logic units using behavioural desing (Mux, decoders, ALU).\n- Parameters.\n\n## Task 2:\n-  **Create a 3-\u003e8 Decoder with enable.**\n-  **N-bit comparator with 3 inputs, there are 2 (2*N) Outputs, outputs are decided according to the task pdt attached.**\n\u003chr\u003e\n\n## Lecture 3 - Intro to:\n- Sequential circuits.\n- Using (posedge, negedge).\n- Video Graphics Array standards.\n- Basic sequential Logic units (D-Latch, D-Flip Flop, T-Flip Flop, 4-bit register with load, up down load coutner).\n\n## Task 3:\n- **Creating a VGA Controller, with 640 * 480 @ 60Hz industry standard, this interfaces with the VGA connector forcing a color to the whole screen pixel array using a parameter.**\n\u003chr\u003e\n  \n## Lecture 4 - Intro to:\n- Universal Asynchronous Receiver / Transmitter (UART) protocol.\n- Generating required baud rate using counter and master clock.\n- Design of the transmitter module using MUX and Counters.\n- Basics of Static Time Analysis (STA).\n- FPGA Intellectual Properties (IP) and Phase-Locked Loop (PLL).\n\n## Task 4:\n- **Implement the transmitter module discussed in the session.**\n- **Design the architecture for a receiver module and implement it with the same baud rate.**\n- **Create a top-level UART module that instantiates both Tx and Rx modules making proper communication**\n- **Make a testbench for the UART module to prove functionality**\n\u003chr\u003e\n\n## Lecture 5 - Intro to:\n- Finite State Machines (FSM).\n- Mealy and Moore machines and their corresponding state diagrams.\n- Implementation of FSM in Verilog using structured steps:\n  - Accurate machine description\n  - Creating the State Diagram. (Define both States and Transitions)\n  - Synthesize the logic. (Implement State memory, Next State logic, Output Logic)\n- Hands-on lab to implement a Sequence Detector that supports overlapping and increments a counter every time the sequence is detected.\n\n## Task 5:\n**No Task for session 5**\n\u003chr\u003e\n\n## Lecture 6 (Final Lecture) - Intro to:\n- Memory addressing.\n- Designing addressing schemes.\n- Using the previously built VGA Controller with active memory to pull pixel RGB values from the memory to display live images.\n- Rescaling VGA standard resolution without affecting timing to overcome memory limitations.\n- RISC-V open-source processor architecture.\n- Assembly code and how a RISC-VI interprets it.\n\n## Final Project:\n**Implement a basic Single Cycle RISC-V processor using Verilog, which interprets Binary Assembly code according to the RISC-V architecture and performs the corresponding operation on the operands.**\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdopebiscuit%2Fieee-digital-ic-design","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdopebiscuit%2Fieee-digital-ic-design","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdopebiscuit%2Fieee-digital-ic-design/lists"}