{"id":29552599,"url":"https://github.com/dotdot0/cpu_4","last_synced_at":"2026-02-08T19:04:19.258Z","repository":{"id":303785109,"uuid":"883583712","full_name":"dotdot0/cpu_4","owner":"dotdot0","description":null,"archived":false,"fork":false,"pushed_at":"2025-07-09T11:17:35.000Z","size":28,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-07-09T12:30:56.720Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/dotdot0.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2024-11-05T08:17:15.000Z","updated_at":"2025-07-09T11:17:39.000Z","dependencies_parsed_at":"2025-07-09T12:33:49.191Z","dependency_job_id":null,"html_url":"https://github.com/dotdot0/cpu_4","commit_stats":null,"previous_names":["dotdot0/cpu_4"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/dotdot0/cpu_4","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dotdot0%2Fcpu_4","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dotdot0%2Fcpu_4/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dotdot0%2Fcpu_4/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dotdot0%2Fcpu_4/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/dotdot0","download_url":"https://codeload.github.com/dotdot0/cpu_4/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dotdot0%2Fcpu_4/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":265703769,"owners_count":23814076,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-07-18T05:11:17.432Z","updated_at":"2026-02-08T19:04:17.908Z","avatar_url":"https://github.com/dotdot0.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 4-Bit CPU with Assembler\nOverview\n\nThis project implements a 4-bit CPU in Verilog, complete with a testbench and an integrated assembler. The assembler simplifies the process of creating testbenches by allowing you to write instructions in a file and automatically generating a testbench for simulation.\nFeatures\n\n    4-Bit CPU: Fully functional CPU designed in Verilog.\n    Assembler: Converts high-level assembly-like instructions into testbench-compatible format.\n    Automated Testbench Generation: No need to manually write testbenches; simply define instructions in a file.\n    Simulation: Use GTKWave to simulate the CPU and visualize outputs.\n\nUsage\n1. Write Instructions\n\nCreate a file (e.g., instructions.txt) with the instructions and opcodes for the CPU.\n2. Generate Testbench\n\nRun the assembler script to generate a testbench:\n\npython assembler.py instructions.txt\n\nThis will output a testbench (e.g., cpu_testbench.v).\n3. Simulate\n\nRun the generated testbench in a Verilog simulator like GTKWave to observe the CPU's behavior:\n\n# Example with a simulator\nvvp cpu_testbench\n\nThen, load the output in GTKWave to analyze signals.\nRequirements\n\n    Verilog Tools: Any Verilog simulator (e.g., ModelSim, Icarus Verilog).\n    GTKWave: For waveform visualization.\n    Python: To run the assembler.\n\nProject Structure\n\n    ├── cpu.v              # 4-bit CPU Verilog implementation\n    ├── cpu_testbench.v    # Testbench for simulation\n    ├── assembler.py       # Assembler script\n    ├── instructions.txt   # Example instruction file\n    ├── README.md          # Project documentation\n\nExample Instruction File\n\n    LOAD R1, 0x3\n    ADD R1, R2\n    SUB R1, R2\n    AND R1, R2\n    OR R1, R2\n    XNOR R1, R2\n    WRITE 0x5, R1\n    SLEEP\n\nFuture Enhancements\n\n    Support for additional opcodes and instructions.\n    Interactive assembler with error handling.\n    Enhanced visualization for complex simulations.\n\nHappy simulating! 🚀\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdotdot0%2Fcpu_4","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdotdot0%2Fcpu_4","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdotdot0%2Fcpu_4/lists"}