{"id":13649304,"url":"https://github.com/dpretet/async_fifo","last_synced_at":"2026-01-12T02:34:14.593Z","repository":{"id":76924495,"uuid":"86497447","full_name":"dpretet/async_fifo","owner":"dpretet","description":"A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog","archived":false,"fork":false,"pushed_at":"2024-04-30T04:54:43.000Z","size":1061,"stargazers_count":258,"open_issues_count":1,"forks_count":76,"subscribers_count":11,"default_branch":"master","last_synced_at":"2024-11-10T00:32:55.958Z","etag":null,"topics":["asic","asic-design","async","cdc","cross-clock-domain","fifo","fifo-cache","fifo-queue","fpga","hdl","icarus-verilog","synthesis","verification","verilator","verilog","verilog-hdl"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/dpretet.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-03-28T19:09:57.000Z","updated_at":"2024-11-09T08:39:46.000Z","dependencies_parsed_at":"2024-01-14T11:00:20.126Z","dependency_job_id":"6bac8f13-14af-4480-baa6-8e9aedbeb5d0","html_url":"https://github.com/dpretet/async_fifo","commit_stats":null,"previous_names":[],"tags_count":6,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fasync_fifo","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fasync_fifo/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fasync_fifo/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fasync_fifo/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/dpretet","download_url":"https://codeload.github.com/dpretet/async_fifo/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258923,"owners_count":21400997,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","asic-design","async","cdc","cross-clock-domain","fifo","fifo-cache","fifo-queue","fpga","hdl","icarus-verilog","synthesis","verification","verilator","verilog","verilog-hdl"],"created_at":"2024-08-02T01:04:56.171Z","updated_at":"2026-01-12T02:34:14.583Z","avatar_url":"https://github.com/dpretet.png","language":"Verilog","readme":"# Asynchronous dual clock FIFO\n\n![CI](https://github.com/dpretet/async_fifo/actions/workflows/ci.yaml/badge.svg?branch=master)\n[![GitHub issues](https://img.shields.io/github/issues/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/issues)\n[![GitHub forks](https://img.shields.io/github/forks/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/network)\n[![GitHub stars](https://img.shields.io/github/stars/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/stargazers)\n[![GitHub license](https://img.shields.io/github/license/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/blob/master/LICENSE)\n\n# Overview\n\nThis repository stores a verilog description of dual clock FIFO. A FIFO is\na convenient circuit to exchange data between two clock domains. It manages\nthe RAM addressing internally, the clock domain crossing and informs the user\nof the FIFO fillness with \"full\" and \"empty\" flags.\n\nIt is widely inspired by the excellent article from Clifford Cummings,\n[Simulation and Synthesis Techniques for Asynchronous FIFO\nDesign](http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf).\n\nThe simulation testcases available use [Icarus Verilog](http://iverilog.icarus.com) and [SVUT](https://github.com/dpretet/svut) tool to run the tests.\n\nThe FIFO is fully functional and used in many successful projects.\n\n# Usage\n\nRTL sources are present in RTL folder under three flavors:\n- `rtl/async_fifo.v`: a basic asynchronous dual-clock FIFO\n- `rtl/async_bidir_fifo.v`: two instance of the first one into a single top level for full-duplex channel\n- `rtl/async_bidir_ramif_fifo.v`: same than previous but with external RAM\n\nThe three FIFOs have a list file to get the associated fileset.\n\nThe testbench in `sim/` provides an example about the instance and the configuration.\n\nAll three top levels have the same parameters:\n- `DSIZE`: the size in bits of the datapath\n- `ASIZE`: the size in bits of the internal RAM address bus. This implies the FIFO can be configured only with power of 2 depth\n- `FALLTHROUGH`: allow to reduce the inner latency and propagate faster the data through the FIFO\n\n\n# License\n\nPermission is hereby granted, free of charge, to any person obtaining a copy of\nthis software and associated documentation files (the \"Software\"), to deal in\nthe Software without restriction, including without limitation the rights to\nuse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies\nof the Software, and to permit persons to whom the Software is furnished to do\nso, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE. imitations under the License.\n","funding_links":[],"categories":["Verilog","Libraries"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdpretet%2Fasync_fifo","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdpretet%2Fasync_fifo","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdpretet%2Fasync_fifo/lists"}