{"id":48448643,"url":"https://github.com/dpretet/svlogger","last_synced_at":"2026-04-06T19:03:08.894Z","repository":{"id":39405768,"uuid":"389047966","full_name":"dpretet/svlogger","owner":"dpretet","description":"SystemVerilog Logger ","archived":false,"fork":false,"pushed_at":"2025-09-30T18:05:44.000Z","size":18,"stargazers_count":19,"open_issues_count":1,"forks_count":3,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-02-01T22:31:37.706Z","etag":null,"topics":["asic","class","fpga","hdl","icarus","logger","logging","simulation","systemverilog","verilog"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/dpretet.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2021-07-24T08:51:09.000Z","updated_at":"2025-12-02T06:39:51.000Z","dependencies_parsed_at":"2023-01-23T02:16:02.840Z","dependency_job_id":null,"html_url":"https://github.com/dpretet/svlogger","commit_stats":null,"previous_names":[],"tags_count":5,"template":false,"template_full_name":null,"purl":"pkg:github/dpretet/svlogger","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fsvlogger","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fsvlogger/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fsvlogger/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fsvlogger/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/dpretet","download_url":"https://codeload.github.com/dpretet/svlogger/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fsvlogger/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31485516,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-06T17:22:55.647Z","status":"ssl_error","status_checked_at":"2026-04-06T17:22:54.741Z","response_time":112,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","class","fpga","hdl","icarus","logger","logging","simulation","systemverilog","verilog"],"created_at":"2026-04-06T19:02:47.794Z","updated_at":"2026-04-06T19:03:08.876Z","avatar_url":"https://github.com/dpretet.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"![CI](https://github.com/dpretet/svlogger/actions/workflows/ci.yaml/badge.svg?branch=main)\n[![GitHub license](https://img.shields.io/github/license/dpretet/svlogger)](https://github.com/dpretet/svlogger/blob/master/LICENSE)\n[![GitHub issues](https://img.shields.io/github/issues/dpretet/svlogger)](https://github.com/dpretet/svlogger/issues)\n[![GitHub stars](https://img.shields.io/github/stars/dpretet/svlogger)](https://github.com/dpretet/svlogger/stargazers)\n[![GitHub forks](https://img.shields.io/github/forks/dpretet/svlogger)](https://github.com/dpretet/svlogger/network)\n[![Twitter](https://img.shields.io/twitter/url/https/github.com/dpretet/svlogger?style=social)](https://twitter.com/intent/tweet?text=Wow:\u0026url=https%3A%2F%2Fgithub.com%2Fdpretet%2Fsvlogger)\n\n# SVLogger\n\nA SystemVerilog logger to help designers to log events in a circuit during a\nsimulation in a consistent way. SVLogger is a simple class, easy to instantiate\nand use, with no dependencies.\n\n## Setup\n\nJust include in source file:\n\n```verilog\n`include \"svlogger.sv\"\n```\n\nand into the fileset:\n\n```\n+incdir+SVLOGGER_PATH\n```\n\nPlease notice this project has been developed and tested with Icarus Verilog 11 and Verilator 5. It\ncan't work with oldest versions. SVlogger could probably work with other (commercial) simulators but\nit never has been tested oustide iverilog and verilator scope.\n\n## How to\n\nFirst instantiate and setup it in a module:\n\n```verilog\n    svlogger mylog;\n\n    initial begin\n        mylog = new(\"MyFSM\", `SVL_VERBOSE_DEBUG, `SVL_ROUTE_TERM);\n    end\n```\n\nThen call a function to print a message:\n\n```verilog\n    always @ (posedge aclk or negedge aresetn) begin\n\n        ...\n            case (fsm)\n                default: begin\n                    mylog.debug(\"Start in IDLE state\");\n                    fsm \u003c= ONE;\n                end\n        ...\n            endcase\n        end\n    end\n```\n\nA complete example of svlogger usage is present in [example](./example) folder.\n\nThe class is setup with three arguments:\n- **name**: the identifier printed first in the log associated to the\n  module under debug.\n- **verbosity**: 0 deactivate all logs, upper values define the filtering level\n  of the logging.\n- **route**: 1 print in console, 2 print in a log file (name.log), 3 in both.\n\n\nFive functions are available to print a message by severity level:\n- ⬜️ **debug**, printed in white\n- 🟦 **info**, printed in blue\n- 🟨 **warning**, printed in yellow\n- 🟪 **critical**, printed in pink\n- 🟥 **error**, printed in red\n\nAnother function named **msg** is available to print a message without prepended\nseverity prefix.\n\n\nIf verbosity is 0, no messages are logged. If equal to 1, everything is logged.\nIf verbosity=2, only info, warning, critical and errors and so on until 5. All\nlogs below the verbosity are discarded, all above are logged.\n\nFor convenience, multiple defines can be used:\n- **\\`SVL_VERBOSE_OFF** (0)\n- **\\`SVL_VERBOSE_DEBUG** (1)\n- **\\`SVL_VERBOSE_INFO`** (2)\n- **\\`SVL_VERBOSE_WARNING** (3)\n- **\\`SVL_VERBOSE_CRITICAL** (4)\n- **\\`SVL_VERBOSE_ERROR** (5)\n\nDefines exist also to define the output routing:\n- **\\`SVL_ROUTE_TERM** (1)\n- **\\`SVL_ROUTE_FILE** (2)\n- **\\`SVL_ROUTE_ALL** (3)\n\nMessages are logged with embedded timeframe. To have a pretty-print of $realtime,\nyou can setup the format with the next trick, for instance in your testbench:\n\n```verilog\n// $timeformat(\u003cunit_number\u003e, \u003cprecision\u003e, \u003csuffix_string\u003e, \u003cminimum field width\u003e);\ninitial $timeformat(-9, 1, \"ns\", 8);\n```\n\nThis should produce a similar output:\n\n```bash\nMyCircuit: ERROR: (@ 406.0ns) Moving in a new state\n```\n\nBy default, the file to log the messages is named with the name attribute passed\nto the constructor. But the filename can be set up with a custom name with a\ntask:\n\n```verilog\n    ...\n    initial begin\n        mylog = new(\"MyFSM\", `SVL_VERBOSE_DEBUG, `SVL_ROUTE_ALL);\n        mylog.set_filename(\"mySuperFSM.txt\");\n    end\n    ...\n```\n\nIf using Verilator, the first file is suppressed and a new file is created; but with\nIcarus Verilog the first file is kept because the tool limitation to use `$system()`.\n\n## Log Merger Tool\n\nSVLogger includes a Python script to merge multiple log files into a single chronological file. This\nis useful when you have logs from multiple modules logging and want to see the complete simulation timeline.\n\n### Usage\n\n```bash\n# Merge specific log files into svlogger.log (default file name)\npython3 svlogger.py file1.txt file2.txt\n\n# Merge all .txt files in a directory\npython3 svlogger.py logs/*.txt --output simulation_run.log\n\n# Scan a directory recursively for all log files\npython3 svlogger.py logs/ --output merged.log\n\n# Verbose mode\npython3 svlogger.py *.txt --output merged.log --verbose\n\n```\n\n### Time Format and Custom Regex\n\nThe script extracts simulation time using Python regular expressions. By default, it looks for the SVLogger format:\n```\n(@ 10.0ns) or (@42us)\n```\n\nThe default regex pattern is: `r\"\\(@\\s*([0-9]+\\.?[0-9]*)([a-zA-Z]+)\\)\"`\n\nYou can customize this with the `--time-pattern` option to match different log formats:\n\n```bash\n# For format [10.5ns]\npython3 svlogger.py logs/ --time-pattern '\\\\[([0-9]+\\\\.?[0-9]*)([a-zA-Z]+)\\\\]'\n\n# For format @10ns (no parentheses)\npython3 svlogger.py logs/ --time-pattern '@([0-9]+\\.?[0-9]*)([a-zA-Z]+)'\n\n# For format time=10.2us\npython3 svlogger.py logs/ --time-pattern 'time=([0-9]+\\.?[0-9]*)([a-zA-Z]+)'\n```\n\n**Note**: The pattern must contain two capture groups:\n1. First group: the numeric value (e.g., `10.5`)\n2. Second group: the time unit (e.g., `ns`, `us`)\n\nSupported time units: ns, us, ms, s, ps, fs (case insensitive)\n\nThe script:\n- Extracts simulation time from each log line\n- Sorts all entries chronologically by converting times to nanoseconds\n- Preserves ANSI color codes\n- Requires only Python 3 standard library (no external dependencies)\n\n## License\n\nThis repo is licensed under MIT license. It grants nearly all rights to use,\nmodify and distribute these sources. However, consider to contribute and provide\nupdates to this core if you add feature and fix, would be greatly appreciated :)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdpretet%2Fsvlogger","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdpretet%2Fsvlogger","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdpretet%2Fsvlogger/lists"}