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All rights reserved._\n\nThis code and related documents are hosted on [GitHub](https://github.com/dries007/FPGAPerformanceSuite) and on [thesis.dries007.net](https://thesis.dries007.net).\n\n## Contents\n\n+ [Documents](Documents): The thesis document and the interim report.\n\n  + [DriesKennes_Thesis_Print.pdf](Documents/DriesKennes_Thesis_Print.pdf): The PDF as originally printed.\n  + [Appendix](Documents/Appendix): All files included in the printed thesis text and appendix.\n  + [Interim_Report](Documents/Interim_Report): All files from the interim report.\n  + [DriesKennes_Thesis_Presentation.pdf](Documents/DriesKennes_Thesis_Presentation.pdf): The thesis defense presentation.\n\n+ [Thesis](Thesis): The source code for the thesis documents.\n+ [ISCAS89](ISCAS89): The ISCAS'89 benchmark set and related materials.\n+ [VHDL](VHDL): All custom VHDL code.\n+ [Results](Results): All output data from our tests.\n+ **[Python](Python): The main software source code.**\n\n## License\n\nAll code in this repository not otherwise marked is released under the terms of the MIT license. See [LICENSE.txt](LICENSE.txt) for the full terms of the this license.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdries007%2Ffpgaperformancesuite","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdries007%2Ffpgaperformancesuite","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdries007%2Ffpgaperformancesuite/lists"}