{"id":16014082,"url":"https://github.com/drom/wast-readmemh","last_synced_at":"2026-01-31T07:31:25.133Z","repository":{"id":145177468,"uuid":"56367370","full_name":"drom/wast-readmemh","owner":"drom","description":"WebAssembly to Verilog data file","archived":false,"fork":false,"pushed_at":"2016-04-16T05:38:05.000Z","size":1,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-06-25T13:04:11.455Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/drom.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2016-04-16T05:30:07.000Z","updated_at":"2023-04-12T07:11:14.000Z","dependencies_parsed_at":null,"dependency_job_id":"f9a379e3-213f-49e8-8321-5c06fee7ed6d","html_url":"https://github.com/drom/wast-readmemh","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/drom/wast-readmemh","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fwast-readmemh","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fwast-readmemh/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fwast-readmemh/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fwast-readmemh/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/drom","download_url":"https://codeload.github.com/drom/wast-readmemh/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fwast-readmemh/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28933224,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-31T04:05:25.756Z","status":"ssl_error","status_checked_at":"2026-01-31T04:02:35.005Z","response_time":128,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-08T15:01:25.970Z","updated_at":"2026-01-31T07:31:25.119Z","avatar_url":"https://github.com/drom.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# wast-readmemh\n\nTakes WebAssembly AST and produces bytecode in Verilog format.\n\nThe Verilog Hardware Description Language (HDL) provides a function `$readmemh()` to load a memory.\n\n## Format\n\nThe syntax of the text file is described in the documentation of the IEEE standard for Verilog.\nFile contains two types of tokens: data and optional addresses.\nThe tokens are separated by whitespace and comments.\nComments may be single-line `//` or multi-line `/* */`, similar to C.\nAddresses are specified by a leading `@` character and are always hexadecimal strings.\nData values are hexadecimal strings.\nData and addresses may contain underscore `_` characters.\nThe syntax supports 4-state logic for data values `(0, 1, x, z)`, where x represents an unknown value and z represents the high impedance value.\n\nIf no address is specified, the data is assumed to start at address 0.\nSimilarly, if data exists before the first specified address, then that data is assumed to start at address 0.\n\nThere are many corner cases which are not explicitly mentioned in the Verilog document.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdrom%2Fwast-readmemh","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fdrom%2Fwast-readmemh","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fdrom%2Fwast-readmemh/lists"}