{"id":13442125,"url":"https://github.com/duskwuff/Xilinx-ISE-Makefile","last_synced_at":"2025-03-20T13:32:31.874Z","repository":{"id":138842311,"uuid":"37999706","full_name":"duskwuff/Xilinx-ISE-Makefile","owner":"duskwuff","description":"An example of how to use the Xilinx ISE toolchain from the command line","archived":false,"fork":false,"pushed_at":"2019-06-30T12:40:19.000Z","size":9,"stargazers_count":59,"open_issues_count":2,"forks_count":21,"subscribers_count":9,"default_branch":"master","last_synced_at":"2024-08-01T03:39:00.153Z","etag":null,"topics":["fpga","xilinx","xilinx-ise"],"latest_commit_sha":null,"homepage":null,"language":"Makefile","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"unlicense","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/duskwuff.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2015-06-24T17:26:18.000Z","updated_at":"2024-02-29T18:41:07.000Z","dependencies_parsed_at":"2023-03-13T10:52:42.515Z","dependency_job_id":null,"html_url":"https://github.com/duskwuff/Xilinx-ISE-Makefile","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/duskwuff%2FXilinx-ISE-Makefile","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/duskwuff%2FXilinx-ISE-Makefile/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/duskwuff%2FXilinx-ISE-Makefile/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/duskwuff%2FXilinx-ISE-Makefile/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/duskwuff","download_url":"https://codeload.github.com/duskwuff/Xilinx-ISE-Makefile/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":221768466,"owners_count":16877642,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","xilinx","xilinx-ise"],"created_at":"2024-07-31T03:01:41.967Z","updated_at":"2025-03-20T13:32:31.866Z","avatar_url":"https://github.com/duskwuff.png","language":"Makefile","funding_links":[],"categories":["HarmonyOS"],"sub_categories":["Windows Manager"],"readme":"Xilinx ISE Makefile\n===================\n\nTired of clicking around in Xilinx ISE? Run your builds from the command line!\n\n\nRequirements\n------------\n\n  * Xilinx ISE, ideally 14.7 (the final version)\n\n  * GNU (or compatible?) Make\n\n    Install this through Cygwin on Windows.\n\n\nCreating a project\n------------------\n\nTo start building a project, you will need to create a file `project.cfg` in\nthe top level of your project. This file is a text file sourced by Make, so\nit consists of `KEY = value` pairs. It must define at least the following keys:\n\n  * `PROJECT`\n\n    The name of the project, used as a name for certain intermediate files, and\n    as the default name for the top-level module and constraints file.\n\n  * `TARGET_PART`\n\n    The full part-speed-package identifier for the Xilinx part to be targeted,\n    e.g. `xc6slx9-2-tqg144`.\n\n  * `XILINX`\n\n    The path to the appropriate binaries directory of the target Xilinx ISE\n    install, e.g.\n    `/cygdrive/c/Xilinx/14.7/ISE_DS/ISE`\n    or\n    `/opt/Xilinx/14.7/ISE_DS/ISE`\n    for typical installs.\n\n  * `VSOURCE` and/or `VHDSOURCE`\n\n    The space-separated names of all Verilog and/or VHDL source files to be\n    used in the project.\n\n    You can define these on multiple lines using `+=`, e.g.\n\n        VSOURCE += foo.v\n        VSOURCE += bar.v\n\nA simple `project.cfg` may thus resemble:\n\n    PROJECT = example\n    TARGET_PART = xc6slx9-2-cpg196\n\n    XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64\n\n    VSOURCE = example.v\n\nA number of other keys can be set in the project configuration, including:\n\n  * `XILINX_PLATFORM`\n\n    The Xilinx name for the platform to build for, e.g. `nt64` or `lin`.\n    `nt64` is used by default for Windows systems, and `lin64` for Linux\n    systems, so you only need to set this if you explicitly need to use the\n    32-bit version of the tools for some reason.\n\n  * `TOPLEVEL`\n\n    The name of the top-level module to be used in the project.\n    (Defaults to `$PROJECT`.)\n\n  * `CONSTRAINTS`\n\n    The name of the constraints file (`.ucf`) to be used for the project.\n    (Defaults to `$PROJECT.ucf`.)\n\n  * `COMMON_OPTS`\n\n    Extra command-line options to be passed to all ISE executables. Defaults to\n    `-intstyle xflow`.\n\n  * `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`,\n    `TRACE_OPTS`, `FUSE_OPTS`\n\n    Extra command-line options to be passed to the corresponding ISE tools. All\n    default to empty.\n\n    Note that `XST_OPTS` will not appear on the command line during\n    compilation, as the XST options are embedded in a script file.\n\n    `MAP_OPTS` and `PAR_OPTS` can be set to `-mt 2` to use multithreading,\n    which may speed up compilation of large designs.\n\n    `BITGEN_OPTS` can be set to `-g Compress` to apply bitstream compression.\n\n  * `PROGRAMMER`\n\n    The name of the programmer to be used for `make prog`. Currently supported\n    values are:\n\n      * `impact`\n\n        Uses Xilinx iMPACT for programming, using a batch file named\n        `impact.cmd` by default. The iMPACT command line may be overridden by\n        setting `IMPACT_OPTS`.\n\n        A typical batch file may resemble:\n\n            setMode -bscan\n            setCable -p auto\n            addDevice -p 1 -file build/projectname.bit\n            program -p 1\n            quit\n\n      * `digilent`\n\n        Uses the Digilent JTAG utility for programming, which must be installed\n        separately. The name of the board must be set as `DJTG_DEVICE`; the\n        path to the djtgcfg executable can be set as `DJTG_EXE`, and the index\n        of the device can be set as `DJTG_INDEX`.\n\n      * `xc3sprog`\n\n        Uses the xc3sprog utility for programming, which must also be installed\n        separately. The cable name must be set as `XC3SPROG_CABLE`; additional\n        options can be set as `XC3SPROG_OPTS`.\n\n\nTargets\n-------\n\nThe Xilinx ISE Makefile implements the following targets:\n\n  * `make default` (or just `make`)\n\n    Builds the bitstream.\n\n  * `make clean`\n\n    Removes the build directory.\n\n  * `make prog`\n\n    Writes the bitstream to a target device. Requires some additional\n    configuration; see below for details.\n\n\nRunning unit tests\n------------------\n\nis a work in progress.\n\n\nUnimplemented features\n----------------------\n\nThe following features are not currently implemented. (Pull requests are\nencouraged!)\n\n  * Generation of SPI or other unusual programming files\n\n  * CPLD synthesis\n\n  * Synthesis tools other than XST\n\n  * Display and/or handling of warnings and errors from `build/_xmsgs`\n\n  * Anything else (open an issue?)\n\n\nLicense\n-------\n\nTo the extent possible under law, the author(s) have dedicated all copyright\nand related and neighboring rights to this software to the public domain\nworldwide. This software is distributed without any warranty.\n\nSee LICENSE.md for details.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fduskwuff%2FXilinx-ISE-Makefile","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fduskwuff%2FXilinx-ISE-Makefile","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fduskwuff%2FXilinx-ISE-Makefile/lists"}