{"id":15060448,"url":"https://github.com/edson-acordi/4bit-microcomputer","last_synced_at":"2025-04-10T05:51:36.629Z","repository":{"id":62815603,"uuid":"234760985","full_name":"edson-acordi/4bit-microcomputer","owner":"edson-acordi","description":"MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for educational purposes and distributed for free under open-source licenses.","archived":false,"fork":false,"pushed_at":"2024-02-29T21:02:02.000Z","size":17049,"stargazers_count":62,"open_issues_count":2,"forks_count":2,"subscribers_count":5,"default_branch":"master","last_synced_at":"2025-03-24T07:05:40.105Z","etag":null,"topics":["4-bit","74hctxxx","alu","asm","assembler","assembly-language","computer","cpu","didactic","digital-electronics","education","harvard-architecture","logic-gates","microcomputer","nibble","open-source","oshw","programming","risc"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/edson-acordi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE-CC-BY-SA-4.0.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2020-01-18T16:14:22.000Z","updated_at":"2025-03-16T20:01:31.000Z","dependencies_parsed_at":"2023-02-19T04:01:10.702Z","dependency_job_id":"26ed1704-adda-4fe9-8e3a-c0ab260685a6","html_url":"https://github.com/edson-acordi/4bit-microcomputer","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/edson-acordi%2F4bit-microcomputer","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/edson-acordi%2F4bit-microcomputer/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/edson-acordi%2F4bit-microcomputer/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/edson-acordi%2F4bit-microcomputer/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/edson-acordi","download_url":"https://codeload.github.com/edson-acordi/4bit-microcomputer/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248166928,"owners_count":21058480,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["4-bit","74hctxxx","alu","asm","assembler","assembly-language","computer","cpu","didactic","digital-electronics","education","harvard-architecture","logic-gates","microcomputer","nibble","open-source","oshw","programming","risc"],"created_at":"2024-09-24T22:58:48.899Z","updated_at":"2025-04-10T05:51:36.606Z","avatar_url":"https://github.com/edson-acordi.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003cimg src=https://img.shields.io/badge/MikroLeo%20Hardware%20Test-96%25-green\u003e \u003cimg src=https://img.shields.io/badge/Hardware%20License-CERN--OHL--S-brightgreen\u003e \u003cimg src=https://img.shields.io/badge/Software%20License-GNU%20GPL-ff0000\u003e \u003cimg src=\"https://img.shields.io/static/v1?label=%F0%9F%8C%9F\u0026message=If%20(you liked OR want to suppport)\u0026style=style=flat\u0026color=9933FF\" alt=\"Star Badge\"\u003e \n\n# MikroLeo #\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/170414182-473c82fa-b765-4346-8646-fb2904b4dfb3.png\" width=\"12%\" height=\"12%\" align=\"left\"\u003e \n\u003cbr /\u003e\n\u003cbr /\u003e\n\n## 4-bit Didactic Microcomputer ##\n\n\u003c!-- This is a comment --\u003e\n\nThe hardware is finished and working. \nHowever, it needs exhaustive testing over a long period to see if the hardware will fail when operating at full speed. It implies that if the hardware fails, the maximum clock speed must be reduced, for example, to 2.5 MHz. \n\nThis project was developed mainly for educational purposes. \n\nI hope it will be a good learning platform for anyone who likes electronics, computers and programming. \n\nSince my first attempts, many efforts have been made to make this project real. \n\nIt is aimed at students, enthusiasts, hackers, professors and anyone who wants to understand or improve their knowledge of electronics and learn how a simple computer works. In addition, it is also an attempt to rescue the story about the beginning of the development of integrated circuits and computers on a single chip, to demonstrate the capabilities that these machines had at that time. \n\nIt is a fully open-source hardware and software project that can be built at home. Only the printed circuit board (PCB) needs to be produced by some company. \n\nFor the next steps, an important thing is to make good documentation for MikroLeo!\n\n***Support this project!*** \n***Help to promote and disseminate the knowledge.*** \n*Copyright (C) 2020-2024 MikroLeo Devs* \n\n---\n\n#### The KiCad project files have been uploaded! ####\n1-[Download KiCad Project](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Kicad-files/MikroLeo/MikroLeo_v0.1901_KiCad.zip \"download\") \n\u003c!--\n[![Download](auxiliary/download.svg)](https://github.com/edson-acordi/4bit-microcomputer/Kicad-files/MikroLeo/MikroLeo/archive/MikroLeo_v0.1901.zip)\n--\u003e\n2-[Download Gerber Files](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Kicad-files/MikroLeo/Gerber/MikroLeo_v0.1901_Rev1.01A_Gerber.zip \"download\") \n\n3-[Download the schematic diagram (pdf file)](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Kicad-files/MikroLeo/MikroLeo_v0.1901_Rev1.01A_sch.pdf \"download\") \n\n4-[Download Bill of Materials (pdf file)](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Docs/MikroLeo_v0.1901_Rev1.01A_BOM.pdf \"download\") \n\u0026nbsp;\u0026nbsp; └─\u003e[Components list made by @vguttmann at the Mouser Electronics store](https://www.mouser.de/ProjectManager/ProjectDetail.aspx?State=EDIT\u0026ProjectGUID=436f56c7-ebe0-469b-b287-6e751369f9cc)\n\n---\n\n#### A Python program to generate machine code has been uploaded ####\n[Python code to \"compile\" asm files](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Compiler/MikroLeoAsm_20221130.py \"download\") \n\n[Windows executable (.exe) to \"compile\" asm files](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Compiler/MikroLeoAsm_20221130.exe \"download\") \n\n---\n\n#### How to transfer compiled program to MikroLeo ####\n[Download documentation (pdf file)](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Docs/How%20to%20transfer%20a%20compiled%20program%20to%20MikroLeo.pdf \"download\") \n\n---\n\n#### The Arduino program to transfer a compiled program to MikroLeo ####\n[Code (Arduino IDE)](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Arduino/MikroLeo_Program_Writring.ino \"download\") \n\n---\n\n**Main Features**:\n- Implements a 4 bit CPU\n- 2k x 16 Program Memory (up to 4k)\n- 2k x 4 RAM (up to 4k)\n- 4 Output Ports (16 outputs)\n- 4 Input Ports (16 inputs)\n- Single Cycle Instruction/RISC\n- Harvard Architecture\n- 3 execution modes:\n * step by step\n * 3MHz (precise time base)\n * adjustable - low clock speed ( $\\approx$ 1 Hz - 200 Hz)\n- No MPU/MCU or complex chips\n- No microcode\n- No stack\n- Indirect addressing to facilitate the implementation of subroutines\n- Program memory implemented with RAM to easy programming\n- It can be programmed using physical input switches or via Arduino/Esp32\n- It accepts 300 and 600 mils memories (for those with old DIP versions)\n- Supercapacitor or battery to keep the program in RAM (for low power version)\n- Built with 74HCTxxx integrated circuits for low power consumption and compatibility with TTL circuits\n- All parts are through-hole for easy assembly\n- All control signals, registers and the program counter are available through the pin header connectors\n- Dual layer Single board with 295.9mm x 196.9mm\n\n# MikroLeo Architecture #\nNote that some buffers are used to allow viewing the contents of registers at any time, since this project is mainly intended for educational purposes. \nReset Vector: 0x000 \n\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/209601697-8584d494-3a72-4378-b84d-aec4b7549ddc.png\" width=\"90%\" height=\"90%\"\u003e\n\n\n# The MikroLeo Instruction Set #\n\nAlthough MikroLeo has only 20 instructions, using the AMODE bit (b14) and the modifier bits (b13:b12), it is possible to encode 64 combinations of instructions, as can be seen below.\n\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/209602107-249cf7d2-7620-4bca-998e-eca0196f1bd0.png\" width=\"90%\" height=\"90%\"\u003e \n\n## Instruction Set explanation and examples ##\n\nIn binary, the Instruction Word is coded as,\n\nROMH (Most significant byte of program memory): \n| \u003csub\u003eb15\u003c/sub\u003e | \u003csub\u003eb14\u003c/sub\u003e | \u003csub\u003eb13\u003c/sub\u003e| \u003csub\u003eb12\u003c/sub\u003e| \u003csub\u003eb11\u003c/sub\u003e | \u003csub\u003eb10\u003c/sub\u003e | \u003csub\u003eb9\u003c/sub\u003e | \u003csub\u003eb8\u003c/sub\u003e \n|---------|-----|----|----|------|------|------|------|\n|\u003csub\u003eMICRO2_IN\u003c/sub\u003e|\u003csub\u003eAMODE\u003c/sub\u003e|\u003csub\u003eMOD1\u003c/sub\u003e|\u003csub\u003eMOD0\u003c/sub\u003e|\u003csub\u003eMICRO3\u003c/sub\u003e|\u003csub\u003eMICRO2\u003c/sub\u003e|\u003csub\u003eMICRO1\u003c/sub\u003e|\u003csub\u003eMICRO0\u003c/sub\u003e|\n\nROML (Least significant byte of program memory): \n| \u003csub\u003eb7\u003c/sub\u003e | \u003csub\u003eb6\u003c/sub\u003e | \u003csub\u003eb5\u003c/sub\u003e | \u003csub\u003eb4\u003c/sub\u003e | \u003csub\u003eb3\u003c/sub\u003e | \u003csub\u003eb2\u003c/sub\u003e | \u003csub\u003eb1\u003c/sub\u003e | \u003csub\u003eb0\u003c/sub\u003e | \n|------|------|------|------|--------|--------|--------|--------| \n\u003csub\u003eMAddr3\u003c/sub\u003e|\u003csub\u003eMAddr2\u003c/sub\u003e|\u003csub\u003eMAddr1\u003c/sub\u003e|\u003csub\u003eMAddr0\u003c/sub\u003e|\u003csub\u003eOperand3\u003c/sub\u003e|\u003csub\u003eOperand2\u003c/sub\u003e|\u003csub\u003eOperand1\u003c/sub\u003e|\u003csub\u003eOperand0\u003c/sub\u003e| \n\n$\\text{\\small\\textcolor{brown}{- Note: b15 = bit15 ... b0 = bit0}}$\n\nBelow is more detailed information about the instruction word, \n\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/202838098-64f25d65-caab-41fb-b613-8623593456ad.png\" width=\"55%\" height=\"55%\"\u003e \n\n### Instruction Set Description ### \n\n**LDI - Load with Immediate** \nDescription: Loads the operand value into a register. \nRegisters: ACC, RA, RB or RC \nOperation: Register \u003c─ Operand\n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|----------------|\n| 0x00Xn |0x00 | LDI ACC,n |ZF |\n| 0x10Xn |0x10 | LDI RA,n |- |\n| 0x20Xn |0x20 | LDI RB,n |- |\n| 0x30Xn |0x30 | LDI RC,n |- |\n\nNote: \nThe operand (immediate) is represented by the letter \"n\". \n'X' (in capital letter) means it doesn't matter. \n'x' (in lowercase) is used to represent a hexadecimal number.\n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x0005 | LDI ACC,5 | Load ACC with operand n|\n| 0x1006 | LDI RA,6 | Load RA with operand n|\n| 0x2007 | LDI RB,7 | Load RB with operand n|\n| 0x300a | LDI RC,10 | Load ACC with operand n|\n\nThe MAddr nibble is not used with this instruction, so it is left at 0. \nThe Instruction Word, for example, for LDI RA,6 is coded as,\n```asm\n0x1006\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 6\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 0\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 1\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0001 0000 0000 0110\n ┆ ┆ ┆ └──\u003e Operand = 6\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 0 (OPCode)\n └─────────────────\u003e HiNB = 1 (MICRO2_IN = 0, AMODE = 0, MOD = 1)\n```\n\n**NAND - bitwise Nand** \nDescription: Performs the bitwise Nand operation between ACC with (Operand n, RA, RB or RAM). \nThe result is stored in ACC. \nOperations: \nACC \u003c─ ACC NAND Operand \nACC \u003c─ ACC NAND Register \nACC \u003c─ ACC NAND RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|----------------|\n| 0x01Xn |0x01 | NAND ACC,n |ZF |\n| 0x11XX |0x11 | NAND ACC,RA |ZF |\n| 0x21XX |0x21 | NAND ACC,RB |ZF |\n| 0x31mn |0x31 | NAND ACC,@RAM |ZF |\n| 0x71XX |0x71 | NAND ACC,@R |ZF |\n\nNote: \nThe RAM address for @RAM is pointed by RC:MAddr:LAddr. \nThe RAM address for @R is pointed by RC:RB:RA. \nThe MAddr is represented by the letter \"m\". \n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|---------------|-|\n| 0x0105 | NAND ACC,5 | NAND operation between the accumulator and the operand and \u003cbr\u003e stores it in ACC |\n| 0x1100 | NAND ACC,RA | NAND operation between the accumulator and register RA and \u003cbr\u003e stores it in ACC |\n| 0x2100 | NAND ACC,RB | NAND operation between the accumulator and register RB and \u003cbr\u003estores it in ACC |\n| 0x310a | NAND ACC,@0x0a | NAND the contents of the RAM address with ACC and stores it \u003cbr\u003e in ACC. In this case, the RAM address = RC:0:a|\n| 0x7100 | NAND ACC,@R | NAND the contents of the RAM address with ACC and stores it \u003cbr\u003e in ACC. In this case, the RAM address = RC:RB:RA|\n\nThe Instruction Word, for example, for NAND ACC,5 is coded as,\n```asm\n0x0105\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 5\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 1\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 0\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0000 0001 0000 0101\n ┆ ┆ ┆ └──\u003e Operand = 5\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 1 (OPCode)\n └─────────────────\u003e HiNB = 0 (MICRO2_IN = 0, AMODE = 0, MOD = 0)\n```\n\n**LDW - Load from RAM Memory** \nDescription: Loads the contents of RAM into ACC. \nOperation: ACC \u003c─ RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|---------------------|----------------|\n| 0x02mn |0x02 | LDW ACC,@RAM |ZF |\n| 0x42XX |0x42 | LDW ACC,@R |ZF |\n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|---------------|-|\n| 0x023b | LDW ACC,@0x3b |Loads the contents of the RAM address (RC:3:b) in ACC |\n| 0x4200 | LDW ACC,@R |Loads the contents of the RAM address (RC:RB:RA) in ACC |\n\nThe Instruction Word, for example, for LDW ACC,@0x3b is coded as,\n```asm\n0x023b\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = b\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 3\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 2\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 0\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0000 0010 0011 1011\n ┆ ┆ ┆ └──\u003e Operand = b\n ┆ ┆ └───────\u003e MAddr = 3\n ┆ └────────────\u003e MICRO = 2 (OPCode)\n └─────────────────\u003e HiNB = 0 (MICRO2_IN = 0, AMODE = 0, MOD = 0)\n```\n\n**LDA - Load Accumulator** \nDescription: Loads the contents of a register into the ACC. \nRegisters: RA, RB or RC \nOperation: ACC \u003c─ Register\n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|---------------|\n| 0x13XX |0x13 | LDA RA |ZF |\n| 0x23XX |0x23 | LDA RB |ZF |\n| 0x33XX |0x33 | LDA RC |ZF |\n\nNote: 'X' means it doesn't matter.\n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x1300 | LDA RA | Load into ACC the content of RA |\n| 0x2300 | LDA RB | Load into ACC the content of RB |\n| 0x3300 | LDA RC | Load into ACC the content of RC |\n\nThe MAddr/LAddr nibble is not used with this instruction, so it is left at 0.\n\nThe Instruction Word, for example, for LDA RA is coded as,\n```asm\n0x1300\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 0\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 3\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 1\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0001 0011 0000 0000\n ┆ ┆ ┆ └──\u003e Operand = 0 (For this instruction, it doesn't matter)\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 3 (OPCode)\n └─────────────────\u003e HiNB = 1 (MICRO2_IN = 0, AMODE = 0, MOD = 1)\n```\n\n**OUTA - Send to OUTA output port** \nDescription: Sends the operand/Register or RAM value to the OUTA output port. \nOperations: \nOUTA \u003c─ Operand \nOUTA \u003c─ ACC \nOUTA \u003c─ RA \nOUTA \u003c─ RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|---------------|\n| 0x04Xn |0x04 | OUTA n |- |\n| 0x14XX |0x14 | OUTA ACC |- |\n| 0x24XX |0x24 | OUTA RA |- |\n| 0x34mn |0x34 | OUTA @RAM |- |\n| 0x74XX |0x74 | OUTA @R |- |\n\nNote: \nThe RAM address for @RAM is pointed by RC:MAddr:LAddr. \nThe RAM address for @R is pointed by RC:RB:RA. \nThe MAddr is represented by the letter \"m\". \n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x0405 | OUTA 5 | Sends the operand to the OUTA port |\n| 0x1400 | OUTA ACC | Sends the ACC to the OUTA port. |\n| 0x2400 | OUTA RA | Sends the RA to the OUTA port. |\n| 0x342a | OUTA @0x2a | Sends the content of RAM to the OUTA port. In this case, the \u003cbr\u003e RAM address = RC:2:a|\n| 0x7400 | OUTA @R | Sends the content of RAM to the OUTA port. In this case, the \u003cbr\u003e RAM address = RC:RB:RA|\n\nThe Instruction Word, for example, for OUTA ACC is coded as,\n```asm\n0x1400\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 0\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 4\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 1\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0001 0100 0000 0000\n ┆ ┆ ┆ └──\u003e Operand = 0\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 4 (OPCode)\n └─────────────────\u003e HiNB = 1 (MICRO2_IN = 0, AMODE = 0, MOD = 0)\n```\n\n**OUTB - Send to OUTB output port** \nDescription: Sends the operand/Register or RAM value to the OUTB output port. \nOperations: \nOUTB \u003c─ Operand \nOUTB \u003c─ ACC \nOUTB \u003c─ RA \nOUTB \u003c─ RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|---------------|\n| 0x05Xn |0x05 | OUTB n |- |\n| 0x15XX |0x15 | OUTB ACC |- |\n| 0x25XX |0x25 | OUTB RA |- |\n| 0x35mn |0x35 | OUTB @RAM |- |\n| 0x75XX |0x75 | OUTB @R |- |\n\nNote: \nThe RAM address for @RAM is pointed by RC:MAddr:LAddr. \nThe RAM address for @R is pointed by RC:RB:RA. \nThe MAddr is represented by the letter \"m\". \n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x0507 | OUTB 7 | Sends the operand to the OUTB port |\n| 0x1500 | OUTB ACC | Sends the ACC to the OUTB port. |\n| 0x2500 | OUTB RA | Sends the RA to the OUTB port. |\n| 0x35f1 | OUTB @0xf1 | Sends the content of RAM to the OUTB port. In this case, the \u003cbr\u003e RAM address = RC:f:1|\n| 0x7500 | OUTB @R | Sends the content of RAM to the OUTB port. In this case, the \u003cbr\u003e RAM address = RC:RB:RA|\n\nThe Instruction Word, for example, for OUTB 7 is coded as,\n```asm\n0x0507\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 7\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 5\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 0\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0001 0101 0000 0111\n ┆ ┆ ┆ └──\u003e Operand = 7\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 5 (OPCode)\n └─────────────────\u003e HiNB = 0 (MICRO2_IN = 0, AMODE = 0, MOD = 0)\n```\n\n**OUTC - Send to OUTC output port** \nDescription: Sends the operand/Register or RAM value to the OUTC output port. \nOperations: \nOUTC \u003c─ Operand \nOUTC \u003c─ ACC \nOUTC \u003c─ RA \nOUTC \u003c─ RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|---------------|\n| 0x06Xn |0x06 | OUTC n |- |\n| 0x16XX |0x16 | OUTC ACC |- |\n| 0x26XX |0x26 | OUTC RA |- |\n| 0x36mn |0x36 | OUTC @RAM |- |\n| 0x76XX |0x76 | OUTC @R |- |\n\nNote: \nThe RAM address for @RAM is pointed by RC:MAddr:LAddr. \nThe RAM address for @R is pointed by RC:RB:RA. \nThe MAddr is represented by the letter \"m\". \n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x0607 | OUTC 0xf | Sends the operand to the OUTC port |\n| 0x1600 | OUTC ACC | Sends the ACC to the OUTC port. |\n| 0x2600 | OUTC RA | Sends the RA to the OUTC port. |\n| 0x3683 | OUTC @0x83 | Sends the content of RAM to the OUTC port. In this case, the \u003cbr\u003e RAM address = RC:8:3|\n| 0x7600 | OUTC @R | Sends the content of RAM to the OUTC port. In this case, the \u003cbr\u003e RAM address = RC:RB:RA|\n\nThe Instruction Word, for example, for OUTC @0x83 is coded as,\n```asm\n0x3683\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 3\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 8\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 6\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 3\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0011 0110 1000 0011\n ┆ ┆ ┆ └──\u003e Operand = 3\n ┆ ┆ └───────\u003e MAddr = 8\n ┆ └────────────\u003e MICRO = 6 (OPCode)\n └─────────────────\u003e HiNB = 3 (MICRO2_IN = 0, AMODE = 0, MOD = 3)\n```\n\n**LDR - Loads a Register with the Accumulator.** \nDescription: Load the contents of the ACC into a register. \nRegisters: RA, RB or RC \nOperation: Register \u003c─ ACC\n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|---------------|\n| 0x17XX |0x17 | LDR RA |- |\n| 0x27XX |0x27 | LDR RB |- |\n| 0x37XX |0x37 | LDR RC |- |\n\nNote: 'X' means it doesn't matter.\n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x1700 | LDR RA | Load into RA the content of ACC |\n| 0x2700 | LDR RB | Load into RB the content of ACC |\n| 0x3700 | LDR RC | Load into RC the content of ACC |\n\nThe MAddr/LAddr nibble is not used with this instruction, so it is left at 0.\n\nThe Instruction Word, for example, for LDR RA is coded as,\n```asm\n0x1700\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 0\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 7\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 1\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0001 0111 0000 0000\n ┆ ┆ ┆ └──\u003e Operand = 0 (For this instruction, it doesn't matter)\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 7 (OPCode)\n └─────────────────\u003e HiNB = 1 (MICRO2_IN = 0, AMODE = 0, MOD = 1)\n```\n\n**CMP - Compare ACC** \nDescription: Performs the comparison between ACC with (Operand n, RA, RB or RAM). \nThe comparison is like a Subtraction, but it doesn't change the ACC.\nThe comparison result can be checked by Flags. \nOperations: \nACC - Operand \nACC - Register \nACC - RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|----------------|\n| 0x08Xn |0x08 | CMP ACC,n |CF,ZF |\n| 0x18XX |0x18 | CMP ACC,RA |CF,ZF |\n| 0x28XX |0x28 | CMP ACC,RB |CF,ZF |\n| 0x38mn |0x38 | CMP ACC,@RAM |CF,ZF |\n| 0x78XX |0x78 | CMP ACC,@R |CF,ZF |\n\nNote: \nThe RAM address for @RAM is pointed by RC:MAddr:LAddr. \nThe RAM address for @R is pointed by RC:RB:RA. \nThe MAddr is represented by the letter \"m\". \n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|---------------|-|\n| 0x0801 | CMP ACC,1 | Compare ACC with operand n |\n| 0x1800 | CMP ACC,RA | Compare ACC with register RA |\n| 0x2800 | CMP ACC,RB | Compare ACC with register RB |\n| 0x38c3 | CMP ACC,@0xc3 | Compare ACC with RAM address. In this case, the RAM \u003cbr\u003e address = RC:c:3 |\n| 0x7800 | CMP ACC,@R | Compare ACC with RAM address. In this case, the RAM \u003cbr\u003e address = RC:RB:RA |\n\nThe Instruction Word, for example, for CMP ACC,1 is coded as,\n```asm\n0x0801\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 1\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 8\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 0\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0000 1000 0000 0001\n ┆ ┆ ┆ └──\u003e Operand = 1\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 8 (OPCode)\n └─────────────────\u003e HiNB = 0 (MICRO2_IN = 0, AMODE = 0, MOD = 0)\n```\n\n**OUTD - Send to OUTD output port** \nDescription: Sends the operand/Register or RAM value to the OUTD output port. \nOperations: \nOUTD \u003c─ Operand \nOUTD \u003c─ ACC \nOUTD \u003c─ RA \nOUTD \u003c─ RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|----------------------|---------------|\n| 0x09Xn |0x09 | OUTD n |- |\n| 0x19XX |0x19 | OUTD ACC |- |\n| 0x29XX |0x29 | OUTD RA |- |\n| 0x39mn |0x39 | OUTD @RAM |- |\n| 0x79XX |0x79 | OUTD @R |- |\n\nNote: \nThe RAM address for @RAM is pointed by RC:MAddr:LAddr. \nThe RAM address for @R is pointed by RC:RB:RA. \nThe MAddr is represented by the letter \"m\". \n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|-------------|-|\n| 0x090b | OUTD 0xb | Sends the operand to the OUTD port |\n| 0x1900 | OUTD ACC | Sends the ACC to the OUTD port. |\n| 0x2900 | OUTD RA | Sends the RA to the OUTD port. |\n| 0x39c3 | OUTD @0xc3 | Sends the content of RAM to the OUTD port. In this case, the \u003cbr\u003e RAM address = RC:c:3|\n| 0x7900 | OUTD @R | Sends the content of RAM to the OUTD port. In this case, the \u003cbr\u003e RAM address = RC:RB:RA|\n\nThe Instruction Word, for example, for OUTD @R is coded as,\n```asm\n0x7900\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 0\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = 9\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 7\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0111 1001 0000 0000\n ┆ ┆ ┆ └──\u003e Operand = 0 (For this instruction, it doesn't matter)\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = 9 (OPCode)\n └─────────────────\u003e HiNB = 7 (MICRO2_IN = 0, AMODE = 1, MOD = 3)\n```\n\n**STW - Store in RAM Memory** \nDescription: Stores the contents of the ACC in RAM. \nOperation: RAM \u003c─ ACC \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|---------------------|----------------|\n| 0x0Amn |0x0A | STW @RAM,ACC |- |\n| 0x4AXX |0x4A | STW @R,ACC |- |\n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|---------------|-|\n| 0x0A1f | STW @0x1f,ACC |Stores the contents of the ACC in RAM (address RC:1:f) |\n| 0x4A00 | STW @R,ACC |Stores the contents of the ACC in RAM (address RC:RB:RA)|\n\nThe Instruction Word, for example, for STW @0x1f,ACC is coded as,\n```asm\n0x0A1f\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = f\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 1\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = A\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 0\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0000 1010 0001 1111\n ┆ ┆ ┆ └──\u003e Operand = f\n ┆ ┆ └───────\u003e MAddr = 1\n ┆ └────────────\u003e MICRO = A (OPCode)\n └─────────────────\u003e HiNB = 0 (MICRO2_IN = 0, AMODE = 0, MOD = 0)\n```\n\n**SUB - Subtract from accumulator** \nDescription: Subtracts from the accumulator the content of (Operand n, RA, RB or RAM) and stores the result in the accumulator. \nOperation: \nACC \u003c─ ACC - Operand \nACC \u003c─ ACC - Register \nACC \u003c─ ACC - RAM \n\n| \u003csub\u003eInstruction Word\u003c/sub\u003e | \u003csub\u003eROMH\u003c/sub\u003e | \u003csub\u003eInstruction\u003c/sub\u003e | \u003csub\u003eAffected Flags\u003c/sub\u003e |\n|------------------|-----------------------|---------------------|----------------|\n| 0x0BXn |0x0B | SUB ACC,n |CF,ZF |\n| 0x1BXX |0x1B | SUB ACC,RA |CF,ZF |\n| 0x2BXX |0x2B | SUB ACC,RB |CF,ZF |\n| 0x3Bmn |0x3B | SUB ACC,@RAM |CF,ZF |\n| 0x7BXX |0x7B | SUB ACC,@R |CF,ZF |\n\n\u003cins\u003eExamples:\u003c/ins\u003e\n\n| **\u003csub\u003eInstruction Word\u003c/sub\u003e** | **\u003csub\u003eInstruction\u003c/sub\u003e** | **\u003csub\u003eComment\u003c/sub\u003e** |\n|------------------|---------------|-|\n| 0x0B0f | SUB ACC,0xf | Subtract from ACC the operand n and store the result in ACC |\n| 0x1B00 | SUB ACC,RA | Subtract from ACC the Register RA and store the result in ACC |\n| 0x2B00 | SUB ACC,RB | Subtract from ACC the Register RA and store the result in ACC |\n| 0x3B9a | SUB ACC,@0x9a | Subtract from ACC the RAM address. In this case, the RAM \u003cbr\u003e address = RC:9:a |\n| 0x7B00 | SUB ACC,@R | Subtract from ACC the RAM address. In this case, the RAM \u003cbr\u003e address = RC:RB:RA |\n\nThe Instruction Word, for example, for SUB ACC,RB is coded as,\n```asm\n0x2B00\n ┆┆┆└──\u003e Least significant Nibble =\u003e Operand[b3:b0] = 0\n ┆┆└───\u003e Second Nibble =\u003e MAddr[b7:b4] = 0\n ┆└────\u003e Third Nibble =\u003e MICRO[b11:b8] = B\n └─────\u003e Most significant Nibble =\u003e HiNB[b15:b12] = 2\n```\nAlso, the instruction word (in binary) to be manually programmed into MikroLeo using physical switches is,\n```asm\n0010 1011 0000 0000\n ┆ ┆ ┆ └──\u003e Operand = 0 (For this instruction, it doesn't matter)\n ┆ ┆ └───────\u003e MAddr = 0 (For this instruction, it doesn't matter)\n ┆ └────────────\u003e MICRO = B (OPCode)\n └─────────────────\u003e HiNB = 2 (MICRO2_IN = 0, AMODE = 0, MOD = 2)\n```\n\n\n...\n\n# Basic Documentation #\n\n**- MikroLeo has four Registers** \n`ACC` - Accumulator (4 bit) - Stores the result of logical and arithmetic operations. Moreover, ACC stores data that is read from or written to RAM. \n`RA` - 4 bit General purpose Register (also used for addressing). \n`RB` - 4 bit General purpose Register (also used for addressing). \n`RC` - 4 bit Special purpose Register used for addressing. \n\n**- Two Flags** \nFlags can only be checked by conditional jump instructions (JPC and JPZ). \n\n`CF` - Carry Flag - It is Set (CF=1) by ADD Instruction if it produces a carry or by SUB/CMP instruction if it results in a borrow. \n`ZF` - Zero Flag - It is affected by operations that modify the contents of the ACC and by CMP instruction. It is Set (ZF=1) if the result of the last operation was zero. \n\nExample of how CF and ZF are Set: \n```asm\nLDI ACC,1 ;Load the operand value into the ACC accumulator.\nADD ACC,0xF ;Performs the addition between the accumulator and the operand and stores the\n ;result in the accumulator.\n```\nThis code does it,\n```\n 0001\n+ 1111\n------- \n 1 0000 \n ↓ ↓ \nCF ACC\n\nAs the value zero is written to ACC, ZF=1.\n```\n\n**- Addressing Modes** \n\n\u003cins\u003e *Immediate* \u003c/ins\u003e \n\nIn immediate addressing, the operand (n) is contained in the lower nibble of the instruction (b3:b0), and it is denoted by Operand, LAddr or OPR. \n\nExample 1: \n```asm\nLDI ACC,1 ;Load the operand value into the ACC accumulator.\n```\nExample 2: \n```asm\nLDI ACC,0xA \n```\nExample 3:\n```asm\nNAND ACC,0 ;Performs the NAND operation between the accumulator and the operand value and\n ;stores the result in the accumulator.\n```\nExample 4:\n```asm\nOUTA 0xF ;Sends the operand value to the OUTA output port.\n```\nExample 5:\n```asm\nCMP ACC,0 ;Performs the comparison between the accumulator and the operand.\n```\nExample 6:\n```asm\nSUB ACC,1 ;Performs the subtraction between the accumulator and the operand and stores\n ;the result in the accumulator.\n```\nExample 7:\n```asm\nADD ACC,5 ;Performs the addition between the accumulator and the operand and stores the\n ;result in the accumulator.\n```\n\n\u003cins\u003e *Register Direct* \u003c/ins\u003e \n\nIn this mode, the operand must be one of the four registers (ACC, RC, RB, RA). Thus, the contents of the lower and medium nibble of the instruction (MAdrr, b7:b4 and LAddr, b3:b0) do not matter. Note that in the LDR instruction, the operand (ACC) is implied. LDR stands for load the Register Rx with ACC, being x={A,B,C}. In the LDA instruction, the operand must be one of the three registers (RC, RB, RA). LDA stands for load the accumulator with one of Rx Registers. Note that in register direct addressing mode, data can be read from or written to a register. \n\nExample 1: \n```asm\nLDR RA ;Loads the value of the ACC accumulator into the RA register.\n```\nExample 2: \n```asm\nLDR RB ;Loads the value of the ACC accumulator into the RB register.\n```\nExample 3: \n```asm\nLDA RA ;Loads the value from the RA Register into the ACC accumulator.\n```\nExample 4: \n```asm\nLDA RC ;Loads the value from the RC Register into the accumulator ACC.\n```\n\n\u003cins\u003e *Register Indirect + Absolute* \u003c/ins\u003e\n\nIn this addressing mode, the `RC` Register points to the high address (b11:b8). The medium (MAddr) and low (LAddr) nibble of the instruction, point to the medium and low address, respectively. \n\nThe final address is composed by `RC:MAddr:LAddr`. \n\nFor example, if: \n```\nRC = 3 \nMAddr = 2 \nLAddr = 1 \n```\nThe address to be accessed is 321h. \nIn the MikroLeo python assembler, absolute addresses (`MAddr:LAddr`) are indicated by an @.\n\nExample 1:\n```asm\nLDI RC,1 ;Loads the operand value into the RC Register.\nOUTA @0xF4 ;Sends the contents of the RAM address pointed to by RC:MAddr:LAddr to output\n ;port A, in this case, the RAM address is RC:MAddr:LAddr = 1F4h.\n```\nExample 2:\n```asm\nLDI RC,3 ;Loads the operand value into the RC Register.\nADD ACC,@0xFC ;Sum the contents of the RAM address pointed to by RC:MAddr:LAddr with ACC\n ;and stores it in ACC. In this case, the RAM address is RC:MAddr:LAddr = 3FCh.\n```\nExample 3: \n```asm\nLDI RC,1 ;Loads the operand value into the RC Register.\nJPI @0x23 ;Jumps to the specified label. In this case, the label address is\n ;RC:MAddr:LAddr = 123h.\n```\nExample 4: \n```asm\nLDI RC,2 ;Loads the operand value into the RC Register.\nCMP ACC,0 ;Compares the contents of ACC with the operand. Is ACC equal to 0?\nJPZ @0x34 ;Jumps to the specified label if ZF=1 (ACC = 0). In this case, the label\n ;address is PCH:MAddr:LAddr = PCH:34h. JPZ does not affect PCH.\n```\nExample 5: \n```asm\nLOOP: \n LDI RC,3 ;Loads the operand value into the RC Register.\n STW @0x21,ACC ;Stores the contents of the accumulator in the RAM address pointed by\n ;RC:MAddr:LAddr, in this case, the RAM address is RC:MAddr:LAddr = 321h.\n LDI RC,\u003eLOOP ;Gets the address of the label, as this code changes the contents of the\n ;Register RC.\n JPI LOOP ;Jumps to the specified label.\n```\nExample 6: \n```asm\nLOOP: \n LDI RC,3 ;Loads the operand value into the RC Register.\n LDW ACC,@0x21 ;Loads the contents of the RAM address pointed by RC:MAddr:LAddr in the\n ;accumulator, in this case, the RAM address is RC:MAddr:LAddr = 321h.\n LDI RC,\u003eLOOP ;Gets the address of the label, as this code changes the contents of the\n ;Register RC.\n JPI LOOP\n```\nExample 7: \n```asm\nLOOP: \n LDI RC,4 ;Loads the operand value into the RC Register.\n CMP ACC,@0x32 ;Compares the contents of ACC with the contents of the RAM address\n ;pointed by RC in this case, the RAM address is RC:MAddr:LAddr = 432h.\n ;Is ACC equal to @432h?\n JPZ LOOP ;Jumps to the specified label if ZF=1 (ACC = @432h).\n```\n\n\u003cins\u003e *Register Indirect* \u003c/ins\u003e\n\nIn this addressing mode, the `RC` Register points to the high address (b11:b8). Likewise, the `RB` Register points to the medium Address (MA) while the `RA` Register points to the low Address (LA). Note that the contents of the lower and medium nibble of the instruction (MAddr, b7:b4 and LAddr, b3:b0) do not matter. \n\nThe final address is composed by `RC:RB:RA`. \n\nFor example, if: \n```Thus, the contents of the lower and medium nibble of the instruction (b7:b4, b3:b0) do\nnot matter.\nRC = 3 \nRB = 2 \nRA = 1 \n```\nThe address to be accessed is 321h. \nIn MikroLeo's python assembler, indirect register addresses (`RC`:`RB`:`RA`) are indicated by an @R.\n\nExample 1:\n```asm\nLDI RC,1 ;Loads the operand value into the RC Register.\nLDI RB,0xF\nLDI RA,4\nOUTA @R ;Sends the contents of the RAM address pointed to by RC:RB:RA to output\n ;port A,\n ;in this case, the RAM address is RC:RB:RA = 1F4h.\n```\nExample 2:\n```asm\nLDI RC,3 ;Loads the operand value into the RC Register.\nLDI RB,0xF\nLDI RA,0xC\nADD ACC,@R ;Sum the contents of the RAM address pointed to by RC:RB:RA with ACC\n ;and stores it in ACC. In this case, the RAM address is RC:RB:RA = 3FCh.\n```\nExample 3: \n```asm\nLDI RC,1 ;Loads the operand value into the RC Register.\nLDI RB,2\nLDI RA,3\nJPI @R ;Jumps to the specified label. In this case, the label address is\n ;RC:RB:RA = 123h.\n```\nExample 4: \n```asm\nLDI RC,2 ;Loads the operand value into the RC Register.\nLDI RB,3\nLDI RA,4\nCMP ACC,0 ;Compares the contents of ACC with the operand. Is ACC equal to 0?\nJPZ @R ;Jumps to the specified label if ZF=1 (ACC = 0). In this case, the\n ;label address is PCH:RB:RA = PCH:34h. JPZ does not affect PCH.\n```\nExample 5: \n```asm\nLOOP: \n LDI RC,3 ;Loads the operand value into the RC Register.\n LDI RB,2\n LDI RA,1\n STW @R,ACC ;Stores the contents of the accumulator in the RAM address pointed by\n ;RC:RB:RA, in this case, the RAM address is RC:RB:RA = 321h.\n LDI RC,\u003eLOOP ;Gets the address of the label, as this code changes the contents of\n ;the Register RC.\n JPI LOOP ;Jumps to the specified label.\n```\nExample 6: \n```asm\nLOOP: \n LDI RC,3 ;Loads the operand value into the RC Register.\n LDI RB,2\n LDI RA,1\n LDW ACC,@R ;Loads the contents of the RAM address pointed by RC:RB:RA in the\n ;accumulator, in this case, the RAM address is RC:RB:RA = 321h.\n LDI RC,\u003eLOOP ;Gets the address of the label, as this code changes the contents of\n ;the Register RC.\n JPI LOOP\n```\nExample 7: \n```asm\nLOOP: \n LDI RC,4 ;Loads the operand value into the RC Register.\n LDI RB,3\n LDI RA,2\n CMP ACC,@R ;Compares the contents of ACC with the contents of the RAM address\n ;pointed by RC in this case, the RAM address is RC:RB:RA = 432h.\n ;Is ACC equal to @432h?\n JPZ LOOP ;Jumps to the specified label if ZF=1 (ACC = @432h).\n```\n\n# Assembler Compiler #\nReleased!\nSee examples how to use...\n\n# How to transfer compiled program to MikroLeo #\n[Download documentation (pdf file)](https://github.com/edson-acordi/4bit-microcomputer/raw/master/Docs/How%20to%20transfer%20a%20compiled%20program%20to%20MikroLeo.pdf \"download\") \n\n# Emulator #\nIn progress...🚧\n\n# Demo #\nMikroLeo in action! \n\nA simple program to make a LED sequencer using the output ports. \n\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/202727866-5db3f19f-970d-4fe7-933c-747d0e465b1a.mp4\" width=\"30%\" height=\"30%\"\u003e\n\nA simple program to initialize an LCD.\n\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/203067797-5abf8e9d-f373-4fb6-898b-bcc9be4d5c2a.mp4\" width=\"30%\" height=\"30%\"\u003e\n\n# Building your own MikroLeo #\n...:soon:\n# Contribution guidelines #\n...:soon:\n# Pictures #\n\nSimulation of the MikroLeo circuit (Made with \"Digital\"): \n[Digital](https://github.com/hneemann/Digital) is free, open source and cross-platform software with a nice interface for digital logic design and circuit simulation.\n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/170560291-f0a1727e-c2dd-46ce-8c69-752019464398.png\" width=\"100%\" height=\"100%\"\u003e\n\nBreadboard: \n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/166626556-bd559537-f371-4d85-87b8-ae23018d6fd7.jpg\" width=\"40%\" height=\"40%\"\u003e \n\nPCB (KiCad 3D viewer): \nTo carry out the project, the [KiCad](https://www.kicad.org/) software was used, an excellent and powerful free and open-source tool for printed circuit board (PCB) designers. \nSize: 295.9mm x 196.9mm \n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/166627152-4c3770eb-8091-40ed-be2d-034289695b60.png\" width=\"60%\" height=\"60%\"\u003e \n\nA simple seven-segment display interface (the PCB has a layout thought for educational purposes, that's why it got big), \nSize: 88.65mm x 141.mm \n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/198721799-a761d863-84b6-472f-9a41-5be4505674a5.png\" width=\"25%\" height=\"25%\"\u003e\n\nPCB Prototype: \n\u003cimg src=\"https://user-images.githubusercontent.com/60040866/166628285-47b3ee24-fd4e-49f8-9bca-21af1cec307d.jpg\" width=\"55%\" height=\"55%\"\u003e \n\n-------------------------------------------\n\n# Development stages #\n\n- [x] - Bibliographic research\n- [x] - Architecture definition\n- [x] - Circuit design\n- [x] - Circuit simulation\n- [x] - Prototype assembly on breadboard\n- [x] - Printed circuit board design\n- [x] - Prototype assembly on PCB\n- [ ] - Final Tests\n\n\n# History and Motivation #\nSince the time I took an 8086 assembly language programming course and took digital electronics and microprocessors classes in college, this project has been something I've always wanted to do. I'm fascinated by electronics, computers and programming!\n\nThe project started in 2020, and the first usable version was completed on April 20, 2020. \n\nInitially, the development of the project used the [Logisim-Evolution](https://github.com/logisim-evolution/logisim-evolution), and later it was migrated to the [Digital](https://github.com/hneemann/Digital). \n\n#### Some sources of inspiration can be seen at: \n\nhttp://www.sinaptec.alomar.com.ar/2018/03/computadora-de-4-bits-capitulo-1.html \nhttps://www.bigmessowires.com/nibbler/ \nhttps://gigatron.io/ \nhttps://eater.net/ \nhttps://apollo181.wixsite.com/apollo181/specification \nhttps://www.megaprocessor.com/ \nhttp://www.mycpu.eu/ \nhttps://minnie.tuhs.org/Programs/CrazySmallCPU/index.html \n\n# Dedication #\nI dedicate this project to my beloved son, Leonardo Pimentel Acordi. \n\n# Acknowledgements #\n\n### The authors would like to thank: \n- The IFPR (Instituto Federal do Paraná), CNPq (Conselho Nacional de Desenvolvimento Científico e Tecnológico) and Fundação Araucária for the partial funding and support for this project.\n\n- The RENESAS (https://www.renesas.com/br/en) for sending me memory samples for tests with MikroLeo. \n\n- All people from the Github community and externals who support this project.\n\n# Sponsor #\nStarting with revision 1.02A (which will be finalized soon) MikroLeo has gained a sponsor for the printed circuit board, the PCBWAY company, a serious company that produces high-quality PCBs. \nhttps://www.pcbway.com/\n\n# Authors #\n\n\u003eEdson Junior Acordi \nMatheus Fernando Tasso \nCarlos Daniel de Souza Nunes \n\n# License #\n\n**Hardware:** Licensed under CERN-OHL-S v2 or any later version \nhttps://ohwr.org/cern_ohl_s_v2.txt\n\n**Software:** Licensed under GNU GPL v3 \nhttps://www.gnu.org/licenses/gpl-3.0.txt\n\n**Documentation:** Licensed under CC BY-SA 4.0 \nhttps://creativecommons.org/licenses/by-sa/4.0/ \n\n\u003e***Note:*** \nAs this project is intended for educational purposes, I have decided to use the CERN-OHL-S license for hardware to ensure that it is always free, contributing, promoting and disseminating the essential knowledge. As such, all hardware derived from it will also be open source! \nLikewise, for the software, the GNU GPL license was used.\n\n## Contact ##\n\n***Note:*** If you have any questions, please consider opening a discussion first, as your question may be helpful to others. If you want to report a bug, please open an issue. \nYou can also contact me via email: [mikroleo.cpu@gmail.com](mailto:mikroleo.cpu@gmail.com)\n\n## Visitor count\n\u003c!-- This is a comment ![Visitor Count](https://profile-counter.glitch.me/{edson-acordi}/count.svg)\n --\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fedson-acordi%2F4bit-microcomputer","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fedson-acordi%2F4bit-microcomputer","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fedson-acordi%2F4bit-microcomputer/lists"}