{"id":19662186,"url":"https://github.com/efeslab/optimus-intel-fpga-bbb","last_synced_at":"2026-03-03T12:42:12.615Z","repository":{"id":82824440,"uuid":"158465613","full_name":"efeslab/optimus-intel-fpga-bbb","owner":"efeslab","description":"Forked from OPAE/intel-fpga-bbb, modified for Optimus FPGA Hypervisor","archived":false,"fork":false,"pushed_at":"2020-01-12T21:52:15.000Z","size":2796,"stargazers_count":6,"open_issues_count":0,"forks_count":1,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-01-10T01:51:34.932Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/efeslab.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":".github/CODEOWNERS","security":null,"support":null,"governance":null,"roadmap":null,"authors":"AUTHORS","dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-11-20T23:48:18.000Z","updated_at":"2022-01-26T19:48:29.000Z","dependencies_parsed_at":null,"dependency_job_id":"c7cc718d-f0f6-4300-afa4-6fe4515aa402","html_url":"https://github.com/efeslab/optimus-intel-fpga-bbb","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/efeslab%2Foptimus-intel-fpga-bbb","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/efeslab%2Foptimus-intel-fpga-bbb/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/efeslab%2Foptimus-intel-fpga-bbb/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/efeslab%2Foptimus-intel-fpga-bbb/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/efeslab","download_url":"https://codeload.github.com/efeslab/optimus-intel-fpga-bbb/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":240970492,"owners_count":19886577,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-11T16:09:53.159Z","updated_at":"2026-03-03T12:42:12.567Z","avatar_url":"https://github.com/efeslab.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Intel FPGA Basic Building Blocks (BBB) #\n\nBasic Building Blocks (BBB) for Intel FPGAs is a suite of application\nbuilding blocks and shims for transforming the CCI-P interface.\n\nFor detailed documentation of the building blocks, please visit the [BBB\nWiki](https://github.com/OPAE/intel-fpga-bbb/wiki \"BBB Wiki\").\n\n## [BBB_cci_mpf](https://github.com/OPAE/intel-fpga-bbb/wiki/BBB_cci_mpf) ##\n\n**Memory Properties Factory (MPF)**: MPF shims may be mixed and matched to\nadd features to the base CCI-P memory interface. Features include: virtual\nmemory, ordered read responses, read/write hazard detection, and masked\n(partial) writes.\n\n## [BBB_ccip_async](https://github.com/OPAE/intel-fpga-bbb/wiki/BBB_ccip_async) ##\n\n**CCI-P Async-shim (CCI-P ASYNC)**: A clock crossing shim, allowing users to\nattach slower-running accelerators to the CCI-P interface.\n\n## BBB_ccip_mux ##\n\n**CCI-P Multiplexer (CCI-P MUX)**: Allows multiple CCI-P compliant agents to\nshare a single CCI-P interface.\n \nThese building blocks are implemented in SystemVerilog RTL and C or C++.\n\n# Versions #\n\nInterfaces and scripts in the BBB repository track changes in the [OPAE\nSDK](https://github.com/OPAE/opae-sdk). Master here may require OPAE SDK's\nmaster as well. There are release branches here in the BBB repository\ncorresponding to OPAE SDK releases.\n\n# [Samples and Tutorial](https://github.com/OPAE/intel-fpga-bbb/wiki/Tutorial) #\n\nA tutorial on CCI-P and Basic Building Blocks (BBB) is in the top-level\n[samples](https://github.com/OPAE/intel-fpga-bbb/tree/master/samples)\ndirectory.\n\n# Release Quality #\n\nThe BBBs should be considered reference sample code that customers may use or\nmodify for their own work. No kernel modules are released in the BBB\nproject. All Basic Building Blocks are tested with supplied examples on an\nUbuntu 14.04 64-bit OS machine with an Integrated Xeon-FPGA. All the BBBs are\nknown to work with the OPAE AFU Simulation Environment (ASE). The project\nmust be considered Alpha quality, and must be used \"as-is\".\n\n# How To Contribute #\n\nFeel free to fork, contribute and share your code as-is in accordance with\nthe BSD-3 license. We encourage submitting bug fixes to the repository via a\npull request in line with our [contribution\nguidelines](https://github.com/OPAE/intel-fpga-bbb/blob/master/CONTRIBUTING.md).\n\nThe Intel FPGA Basic Building Blocks (BBB) project uses a recommended\n(minimum) directory structure. All BBBs must start with a ```BBB_```\nprefix. In your pull-requests, please use the following format:\n\n```\n\n\tBBB_\u003cname\u003e\n\t|-- hw          : Hardware must be staged here\n\t|   |-- rtl     :   RTL files\n\t|   |-- sim     :   Simulation files list (if available)\n\t|   `-- par     :   PAR-specific files\n\t|-- sw          : BBB-specific SW code\n\t`-- samples     : Samples showing how to use the BBB\n\n```\n\n**NOTE:**\n\n* For the sake of space do not check in application objects, libraries, or\n  bitstreams into the repository.\n  * In the 'par' directory, check in only Quartus settings snippets.\n  * Do the same for SDC files.\n  * Do not check in Quartus projects here.\n* Please provide a list of required files for 'par' and 'sim'.\n* If the BBB requires a common set of steps, please consider providing SW\n  helper functions that can be reused.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fefeslab%2Foptimus-intel-fpga-bbb","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fefeslab%2Foptimus-intel-fpga-bbb","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fefeslab%2Foptimus-intel-fpga-bbb/lists"}