{"id":13773842,"url":"https://github.com/eirikpre/VSCode-SystemVerilog","last_synced_at":"2025-05-11T06:31:36.807Z","repository":{"id":38150924,"uuid":"117558978","full_name":"eirikpre/VSCode-SystemVerilog","owner":"eirikpre","description":"SystemVerilog support in VS Code","archived":false,"fork":false,"pushed_at":"2024-10-24T20:03:20.000Z","size":4628,"stargazers_count":127,"open_issues_count":36,"forks_count":50,"subscribers_count":11,"default_branch":"master","last_synced_at":"2024-10-26T06:56:49.755Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"TypeScript","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/eirikpre.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-01-15T14:58:15.000Z","updated_at":"2024-10-24T20:03:25.000Z","dependencies_parsed_at":"2024-10-25T00:24:01.195Z","dependency_job_id":"7fac006c-e09d-4a3c-b564-9ac0f2ee45d5","html_url":"https://github.com/eirikpre/VSCode-SystemVerilog","commit_stats":null,"previous_names":[],"tags_count":46,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/eirikpre%2FVSCode-SystemVerilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/eirikpre%2FVSCode-SystemVerilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/eirikpre%2FVSCode-SystemVerilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/eirikpre%2FVSCode-SystemVerilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/eirikpre","download_url":"https://codeload.github.com/eirikpre/VSCode-SystemVerilog/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225021896,"owners_count":17408511,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-03T17:01:20.774Z","updated_at":"2024-11-17T09:30:22.004Z","avatar_url":"https://github.com/eirikpre.png","language":"TypeScript","readme":"[![](https://img.shields.io/visual-studio-marketplace/v/eirikpre.systemverilog?color=%2346bd19)](https://marketplace.visualstudio.com/items?itemName=eirikpre.systemverilog)\n[![](https://img.shields.io/visual-studio-marketplace/i/eirikpre.systemverilog)](https://marketplace.visualstudio.com/items?itemName=eirikpre.systemverilog)\n![](https://img.shields.io/visual-studio-marketplace/stars/eirikpre.systemverilog)\n[![](https://img.shields.io/github/actions/workflow/status/eirikpre/VSCode-SystemVerilog/test.yaml)](https://github.com/eirikpre/VSCode-SystemVerilog/actions?query=workflow%3ATest+branch%3Amaster)\n\n# SystemVerilog - Language Support\n\nThis VS Code extension provides features to read, navigate and write SystemVerilog code much faster.\n\n## Features\n\n- Elaborate [syntax highlighting](#examples)\n- Go to symbol in document (`Ctrl+Shift+O`)\n- Go to symbol in workspace folder (indexed modules/interfaces/programs/classes/packages) (`Ctrl+T`)\n- Go to definition (_works for module/interface/program/class/package names and for ports too!_) (`Ctrl+LeftClick`)\n- Find references (_works for module/interface/program/class/package names and for ports too!_) (`Ctrl+LeftClick`)\n- Quick-start on already indexed workspaces\n- Code snippets for many common blocks\n- Instantiate module from already indexed module\n- Linter capabilites with simulators ([more info on the wiki](https://github.com/eirikpre/VSCode-SystemVerilog/wiki))\n- Fast real-time error identification through an integrated SystemVerilog parser and IntelliSense (fully accurate to IEEE Standard 1800-2017)\n- If you find a bug or would like a feature, request it as an [Issue](https://github.com/eirikpre/VSCode-SystemVerilog/issues) or submit a [Pull Request](https://github.com/eirikpre/VSCode-SystemVerilog/pulls)\n\n## Examples\n\n### Syntax Highlighting\n\n![Syntax Highlighting Example](resources/syntax_example_adder.png)\n\n### Go To Definition\n\n![Go To Definition Example](resources/goToDef_demo.gif)\n\n### Find References\n\n![Find References Example](resources/find_references.gif)\n\n### Module Instantiation\n\n![Module Instantiation Example](resources/moduleInit_demo.gif)\n\n## Recommendations\n\n- If you have netlists in your workspace you can exclude them in the settings with `systemverilog.excludeIndexing`, e.g.: `**/syn/**`\n- When running in workspaces with a large number of files, the `systemverilog.documentSymbolsPrecision` setting may need to be reduced down to 'full_no_references'. Doing this will turn off the 'find references' feature which will dramatically speedup the parsing.\n- When you have large files, the `systemverilog.maxLineCountIndexing` setting can be tuned to prevent full parsing of these files, which will improve extension performance.\n- _Disclaimer_: This is not a functional tool that will compile and simulate HDL, but it will make it easier and more user-friendly to write and navigate SystemVerilog and Verilog.\n\n## Settings\n\n- `systemverilog.includeIndexing`: _Array_, Files included for indexing \\([glob pattern](https://code.visualstudio.com/docs/editor/glob-patterns)\\). Examples:\n  - Include files within the workspace's rtl folder (`*` at front of pattern denotes path is relative to workspace root): `**/rtl/**/*.{sv,v,svh,vh}`\n  - Add all files with a '.svp' extension: `**/*.svp`\n  - Add files only when in a specific workspace: `/abs/path/to/workspace/rtl/**/*.{sv,v,svh,vh}`\n- `systemverilog.disableIndexing`: _Boolean_, Disable indexing\n- `systemverilog.excludeIndexing`: _String_, Exclude files from indexing based on a [glob pattern](https://code.visualstudio.com/docs/editor/glob-patterns). Examples:\n  - Exclude all files in the 'synth' folder: `**/synth/*`\n  - Exclude more than one folder: `**/{synth,pnr}/**`\n  - Exclude .v files in the 'compile' folder: `**/compile/*.v`\n  - Exclude .v files in the 'compile' dir and exclude all files in the 'synth' folder: `{**/synth/**,**/compile/*.v}`\n- `systemverilog.forceFastIndexing`: _Boolean_, Use fast regular expression parsing\n- `systemverilog.enableIncrementalIndexing`: _Boolean_, Enable incremental indexation as files are opened\n- `systemverilog.parallelProcessing`: _Integer_, Number of files to process in parallel during indexing\n- `systemverilog.forceFastIndexing`: _Boolean_, force indexer to bo basic parsing. Good for when the extension takes too long to initialize.\n- `systemverilog.enableIncrementalIndexing`: _Boolean_, Enable incremental indexation as you open files.\n- `systemverilog.maxLineCountIndexing`: _Boolean_, When indexing a file, if the line count is larger than this number, _fast_ indexing will be used to improve symbol lookup performance, as fewer symbols will be parsed.\n- `systemverilog.documentSymbolsPrecision`: _String_, The level of detail the parser should use when looking for symbols:\n  - _full_: detect blocks, ports, parameters, classes, methods, typedefs, defines, labels, instantiations, assertions, and _references across files_.\n  - _full_no_references_: detect blocks, ports, parameters, classes, methods, typedefs, defines, labels, instantiations, and assertions.\n  - _declarations_: detect blocks, ports, parameters, classes, methods, typedefs, and defines.\n  - _fast_: detect only common blocks (module, class, interface, package, program) without hierarchy.\n- `systemverilog.antlrVerification`: _Boolean_, Use ANTLR parser to verify code in real-time\n- `systemverilog.verifyOnOpen`: _Boolean_, Run ANTLR verification on all files when opened.\n- `systemverilog.launchConfigurationVerilator`: _String_, Command to run when launching verilator\n  - Default: _verilator --sv --lint-only --language 1800-2012 --Wall_\n  - If not in path, replace _verilator_ with the appropriate command\n- `systemverilog.launchConfigurationVCS`: _String_, Command to run when launching VCS\n  - Default: _vcs_\n  - If not in path, replace _vcs_ with the appropriate command\n- `systemverilog.launchConfigurationVerible`: _String_, Command to run when launching Verible\n  - Default: _verible-verilog-lint_\n  - If not in path, replace _verible-verilog-lint_ with the appropriate command\n- `systemverilog.excludeCompiling`: _String_, Files excluded from compiling when saved based on a [glob pattern](https://code.visualstudio.com/docs/editor/glob-patterns)\n- `systemverilog.compileOnSave`: _Boolean_, Compile files when saved\n  - Default: `true`\n- `systemverilog.compilerType`: _String_, Dropdown list to select a compiler type\n  - Default: `Verilator`\n- `systemverilog.trace.server`: _String_, Dropdown to select verbosity of LSP message tracing\n- `systemverilog.compileOnOpen`: _Boolean_, Compile all files when opened\n  - Default: `false`\n\n### Customizations\n\nUse the provided settings in a user or workspace `settings.json` as appropriate. Here are a few examples:\n\n```json\n{\n  \"editor.bracketPairColorization.enabled\": true, // turn on bracket pair coloring\n  \"editor.guides.bracketPairs\": \"active\", // turn on bracket pair guides\n  // Change theme default colors for specific tokens\n  // To find tokens use: https://code.visualstudio.com/api/language-extensions/syntax-highlight-guide#scope-inspector\n  \"editor.tokenColorCustomizations\": {\n    // Customize per theme or globally\n    \"[Theme Name]\": {\n      \"textMateRules\": [\n        {\n          // Workaround: Extension marks escaped identifiers as regular expressions to prevent bracket matching,\n          //             so recoloring it back to identifier color\n          \"scope\": [\"string.regexp.identifier.systemverilog\"],\n          \"settings\": {\n            \"foreground\": \"#e06c75\"\n          }\n        }\n      ]\n    }\n  },\n  // Customize formatting command to suite preferences\n  \"systemverilog.formatCommand\": \"verible-verilog-format --assignment_statement_alignment=preserve --case_items_alignment=infer --class_member_variables_alignment=infer --formal_parameters_alignment=preserve --formal_parameters_indentation=indent --named_parameter_alignment=flush-left --named_parameter_indentation=indent --named_port_alignment=flush-left --named_port_indentation=indent --net_variable_alignment=preserve --port_declarations_alignment=preserve --port_declarations_indentation=indent\",\n  // Add additional file extensions to associate with SystemVerilog and include them in the indexing\n  \"files.associations\": {\n    \"*.svi\": \"systemverilog\",\n    \"*.svp\": \"systemverilog\",\n    \"*.pkg\": \"systemverilog\"\n  },\n  \"systemverilog.includeIndexing\": [\"**/*.{sv,v,svh,vh,svi,svp,pkg}\"]\n}\n```\n\n### Handling Spaces In Executable Paths\n\nPlease exercise caution when setting an executable path in the settings, such as the case with  `systemverilog.formatCommand`, `systemverilog.launchConfigurationVerilator`, `systemverilog.launchConfigurationVCS`, and `systemverilog.launchConfigurationVerible`. Any spaces will be assumed to be arguments and not the executable itself. In Windows, for example, you might have an executable configured as follows:\n\n```json\n\"systemverilog.formatCommand\" : \"C:\\\\Program Files\\\\verible\\\\bin\\\\verible-verilog-format --case_items_alignment=infer\"\n```\n\nBecause of the space in 'Program Files', the extension will infer that the executable is `C:\\\\Program` with two arguments: `Files\\\\verible\\\\bin\\\\verible-verilog-format` and `--case_items_alignment=infer`. This breaks the executable path. There are a couple solutions for tihs:\n\n1. (Prefered) Add the executable to your PATH and call it directly.\n  - [Windows instructions](https://www.computerhope.com/issues/ch000549.htm)\n  - [Linux Instructions](https://phoenixnap.com/kb/linux-add-to-path)\n  - [Mac Instructions](https://www.architectryan.com/2012/10/02/add-to-the-path-on-mac-os-x-mountain-lion/#.Uydjga1dXDg)\n\n```json\n\"systemverilog.formatCommand\" : \"verible-verilog-format --case_items_alignment=infer\"\n```\n\n2. If you can't edit your path (maybe because of privileges), then don't use spaces in paths. Either move the executable to a different location with no spaces, or (in the case of windows) you can use [DOS short names](https://superuser.com/questions/348079/how-can-i-find-the-short-path-of-a-windows-directory-file) as follows:\n\n```json\n\"systemverilog.formatCommand\" : \"C:\\\\PROGRA~1\\\\verible\\\\bin\\\\verible-verilog-format --case_items_alignment=infer\"\n```\n\n\n\n\n\n## Known Issues\n\n- Initial indexing might hog CPU/RAM when looking through files in very large workspaces\n\n## Future\n\n- Tree view of module hierarchy\n- References document\n- Back-end Language server for SystemVerilog\n- Update workspace state to save to [storagePath](https://code.visualstudio.com/api/advanced-topics/remote-extensions#persisting-extension-data-or-state)\n\n## Contributing\n\n- If you want to contribute with the project please fork this repository, clone it, make changes (preferably in a branch other than master) and finally create a Pull Request (more details [here](https://guides.github.com/activities/forking/)).\n- To debug the extension locally first install the required dependencies (in the repository's root directory):\n\n```bash\nnpm install\n```\n\n- Then compile the project at least once (this will generate the SystemVerilog lexer and parser in `src\\compiling\\ANTLR\\grammar\\build`):\n\n```bash\nnpm run compile\n```\n\n- Finally, run the \"Client + Server\" run configuration:\n\n![Debug configuration](resources/client_server_configuration.png)\n\n## Release Notes\n\nSee the [changelog](CHANGELOG.md)\n","funding_links":[],"categories":["Digital Design"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Feirikpre%2FVSCode-SystemVerilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Feirikpre%2FVSCode-SystemVerilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Feirikpre%2FVSCode-SystemVerilog/lists"}