{"id":21402433,"url":"https://github.com/elvircrn/MIC-1","last_synced_at":"2025-09-05T06:31:52.228Z","repository":{"id":91018517,"uuid":"78125567","full_name":"elvircrn/MIC-1","owner":"elvircrn","description":"A microprocessor implemented in VHDL","archived":false,"fork":false,"pushed_at":"2025-01-23T15:35:51.000Z","size":5304,"stargazers_count":0,"open_issues_count":1,"forks_count":1,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-03-16T16:25:33.134Z","etag":null,"topics":["fpga","logic-programming","processor-architecture","vhdl","xilinx"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/elvircrn.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-01-05T15:40:53.000Z","updated_at":"2025-01-23T15:35:55.000Z","dependencies_parsed_at":null,"dependency_job_id":"99ace15e-9e07-4f4e-a8cb-c7aeae819c79","html_url":"https://github.com/elvircrn/MIC-1","commit_stats":null,"previous_names":["elvircrn/mic-1","elvircrn/80085"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/elvircrn/MIC-1","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/elvircrn%2FMIC-1","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/elvircrn%2FMIC-1/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/elvircrn%2FMIC-1/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/elvircrn%2FMIC-1/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/elvircrn","download_url":"https://codeload.github.com/elvircrn/MIC-1/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/elvircrn%2FMIC-1/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":273722729,"owners_count":25156300,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-09-05T02:00:09.113Z","response_time":402,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","logic-programming","processor-architecture","vhdl","xilinx"],"created_at":"2024-11-22T15:37:35.055Z","updated_at":"2025-09-05T06:31:52.195Z","avatar_url":"https://github.com/elvircrn.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# MIC-1\n\n![Alt text](/80085.jpg?raw=true)\n\n## Interpreter koda\n\nOvaj kod sluzi za prevodjenje mikroasemblerskih instrukcija u binarno-enkodiranu instrukciju koju ogledni procesor moze koristiti. \nPrimjer koristenja:\n\n```cpp\n    init(); // Mora se pozvati!!!\n\n    std::vector\u003cstd::pair\u003cint, std::string\u003e\u003e rets =\n    {\n        { 1, \"ac := ac + (1);\" },\n        { 2, \"ac := ac + (1);\" },\n        { 3, \"ac := ac + (1);\" },\n        { 4, \"rd; goto 82\" },\n        { 80, \"mar := ir; rd;\" },\n        { 81, \"b := (0); rd;\" },\n        { 82, \"a := mbr;\" },\n        { 83, \"alu := a; if z then goto 88;\" },\n        { 84, \"alu := a ^ (1); if z then goto 86\" },\n        { 85, \"b := b + ac;\" },\n        { 86, \"ac := ac + ac;\" },\n        { 87, \"a := rshift ( a ); goto 83;\" },\n        { 88, \"ac := b;\" }\n    };\n\n    for (auto \u0026instr : rets)\n        std::cout \u003c\u003c std::setw(5) \u003c\u003c instr.first \u003c\u003c \" =\u003e \\\"\" \u003c\u003c  parse(instr.second) \u003c\u003c \"\\\",\\n\";\n```\n\nKod iznad implementira MULD m instrukciju, pri cemu je ac := 3 na pocetku. Output ovog primjera je:\n\n```cpp\n    1 =\u003e \"00000000000100010000000100000000\",\n    2 =\u003e \"00000000000100010000000100000000\",\n    3 =\u003e \"00000000000100010000000100000000\",\n    4 =\u003e \"01110000010000000000000001010010\",\n   80 =\u003e \"00010000110000000011001100000000\",\n   81 =\u003e \"00010000010110110000000000000000\",\n   82 =\u003e \"10010000000110100000000000000000\",\n   83 =\u003e \"01010000000000000000101001011000\",\n   84 =\u003e \"01001000000000000000101001010110\",\n   85 =\u003e \"00000000000110110001101100000000\",\n   86 =\u003e \"00000000000100010001000100000000\",\n   87 =\u003e \"01110010000110100000101001010011\",\n   88 =\u003e \"00010000000100010000101100000000\"\n```\nkoji se stavlja u ROM komponentu oglednog procesora. Ovaj skup instrukcija je uspjesno testiran na VHDL test benchu oglednog procesora.\n\nLimitacije:\n* Konstante 1, -1 i 0 se obiljezavaju sa (+1), (0), (-1) respektivno\n* Umjesto band koristiti ^ operator\n\nKod je testiran sa 10ak drugih instrukcija, no autor je svjestan velike mogucnosti pojavljivanja bugova. Takodje je potrebno imati u vidu da je kod\npisan u malom vremenskom periodu.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Felvircrn%2FMIC-1","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Felvircrn%2FMIC-1","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Felvircrn%2FMIC-1/lists"}