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RAM      .         |          |  |          |\n       .              .   $d800 +----------+  |          |\n       |              |         |   SID    |  |          |\n $0002 +--------------+         |registers |  |          |\n       | I/O port DR  |   $d400 +----------+  |          |\n $0001 +--------------+         |   VIC    |  |          |\n       | I/O port DDR |         |registers |  |          |\n $0000 +--------------+   $d000 +----------+  +----------+\n\n\n\n## CIA #1 Progress Report\n\n### 0xDC00 \nDone\n\n### 0xDC01\nDone\n\n### 0xDC02\nNo need to implement\n\n### 0xDC03\nNo need to implement\n\n### 0xDC04\nSimple bind\n\n### 0xDC05\nSimple bind\n\n### 0xDC06\nSimple bind\n### 0xDC07\nSimple bind\n\n### 0xDC08\nNo need to implement\n### 0xDC09\nNo need to implement\n### 0xDC0A\nNo need to implement\n### 0xDC0B\nNo need to implement\n\n\n\n### 0xDC0C\nTODO\nSerial shift register. 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