{"id":23870104,"url":"https://github.com/engineermichael/modelsim-altera-project-electronics-","last_synced_at":"2026-02-26T21:04:40.180Z","repository":{"id":260214033,"uuid":"124948481","full_name":"EngineerMichael/ModelSim-Altera-Project-Electronics-","owner":"EngineerMichael","description":"⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code. ","archived":false,"fork":false,"pushed_at":"2025-02-24T01:30:31.000Z","size":5482,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"master","last_synced_at":"2025-11-12T21:07:07.781Z","etag":null,"topics":["altera-de1","altera-fpga","altera-quartus","modelsim","synchronous-counter","vhdl-code"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/EngineerMichael.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-03-12T20:37:49.000Z","updated_at":"2025-02-24T01:30:34.000Z","dependencies_parsed_at":null,"dependency_job_id":"12363693-fd04-41ef-abf3-3b996cd2d903","html_url":"https://github.com/EngineerMichael/ModelSim-Altera-Project-Electronics-","commit_stats":null,"previous_names":["engineermichael/modelsim-altera-project-electronics-"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/EngineerMichael/ModelSim-Altera-Project-Electronics-","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/EngineerMichael%2FModelSim-Altera-Project-Electronics-","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/EngineerMichael%2FModelSim-Altera-Project-Electronics-/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/EngineerMichael%2FModelSim-Altera-Project-Electronics-/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/EngineerMichael%2FModelSim-Altera-Project-Electronics-/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/EngineerMichael","download_url":"https://codeload.github.com/EngineerMichael/ModelSim-Altera-Project-Electronics-/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/EngineerMichael%2FModelSim-Altera-Project-Electronics-/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29872674,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-26T21:01:59.805Z","status":"ssl_error","status_checked_at":"2026-02-26T21:00:42.555Z","response_time":89,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera-de1","altera-fpga","altera-quartus","modelsim","synchronous-counter","vhdl-code"],"created_at":"2025-01-03T13:52:17.047Z","updated_at":"2026-02-26T21:04:40.143Z","avatar_url":"https://github.com/EngineerMichael.png","language":null,"readme":"# ModelSim-Altera-Project-Electronics-\n⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code. \n\nModelSim-Altera-Project-Electronics\n\nOverview\n\nModelSim-Altera-Project-Electronics is a simulation project designed to execute and verify a Synchronous Counter with both Asynchronous and Synchronous Reset capabilities using VHDL (VHSIC Hardware Description Language). The project focuses on implementing counters of varying bit widths: 2-bit, 4-bit, 6-bit, and 11-bit. The counter designs are intended for simulation in the ModelSim-Altera environment, which is commonly used for FPGA and ASIC design verification.\nThe project aims to provide hands-on experience in designing and testing digital counters with different reset behaviors and bit widths, while also leveraging the powerful simulation capabilities of ModelSim-Altera.\nThis project is licensed under the GNU General Public License v3.0.\nFeatures\t\n•\tSynchronous Counter: A counter that increments on each clock cycle and is reset either synchronously or asynchronously.\t\n•\tBit Width Variations: Implementations for 2-bit, 4-bit, 6-bit, and 11-bit counters.\t\n•\tReset Types:\t\n•\tSynchronous Reset: Reset is controlled by the clock and only occurs on specific clock edges.\t\n•\tAsynchronous Reset: Reset can occur independently of the clock signal.\t\n•\tVHDL Code: All designs are implemented using VHDL for hardware description and simulation.\t\n•\tModelSim-Altera Simulation: The project is designed for simulation in the ModelSim-Altera environment, enabling step-by-step debugging and verification of the counter designs.\nInstallation\nPrerequisites\nBefore running the simulation, ensure that the following software is installed on your system:\t\n•\tModelSim-Altera: This is the primary simulation tool used for running the VHDL code. You can download it from the official Intel website.\t\n•\tVHDL Compiler: Ensure that VHDL files are compiled within the ModelSim-Altera environment.\t\n•\tGNU Make (optional): If you wish to automate building and simulation steps via scripts.\nSteps to Download and Set Up the Project\t\n1.\tClone the repository:\ngit clone https://github.com/yourusername/ModelSim-Altera-Project-Electronics.gitcd ModelSim-Altera-Project-Electronics\n\t\n2.\tOpen ModelSim-Altera:\n   •\tLaunch ModelSim-Altera from your applications or terminal, depending on your operating system.\n3.\tCreate a New Project in ModelSim:\n   •\tOpen ModelSim and create a new project (File \u003e New \u003e Project).\n  \t•\tSet the working directory to the root of this repository.\n4.\tAdd VHDL Files to the Project:\n   •\tAdd the VHDL files (such as synchronous_counter.vhdl, asynchronous_counter.vhdl, etc.) to your ModelSim project.\n5.\tCompile VHDL Code:\n   •\tUse ModelSim’s “Compile” option to compile the VHDL files. Ensure there are no errors in the compilation output.\nRunning the Simulation\n1.\tLoad the Testbench:\n   •\tEnsure that a testbench is included for each counter design. The testbench will simulate clock signals and reset behavior.\n2.\tStart the Simulation:\n   •\tAfter compilation, launch the simulation by using the “Simulate” option in ModelSim.\n  \t•\tStart the simulation for each counter by applying clock cycles and reset signals as defined in the testbench.\n3.\tObserve Results:\n   •\tYou can observe the counter output on the waveform viewer.\n  \t•\tStep through the simulation to verify the behavior of the counter under both synchronous and asynchronous reset conditions.\n4.\tDebugging:\n   •\tUse ModelSim’s built-in debugging features like signal tracing, breakpoints, and step-through simulation to troubleshoot any issues with your design.\nUsage\n1. Synchronous Counter (2-bit, 4-bit, 6-bit, 11-bit)\nThe counters are implemented with a simple clock-driven increment mechanism. You can test counters of various bit widths by modifying the generic parameters in the VHDL code.\n•\t2-bit Counter: Suitable for smaller designs or as a basic example of a synchronous counter.\n•\t4-bit Counter: A more common counter size used in many digital systems.\n•\t6-bit Counter: Provides more address space, useful for more complex designs.\n•\t11-bit Counter: Useful for systems requiring large counting ranges.\nThe VHDL code for each of these counters can be found in separate files. Each counter implementation follows a similar structure, where the counter increments on the rising edge of the clock and resets based on the provided reset signal.\n\n3. Reset Mechanisms\n•\tSynchronous Reset: The counter is reset to zero on the rising clock edge when the reset signal is active.\n•\tAsynchronous Reset: The counter is reset immediately when the reset signal is active, regardless of the clock signal.\nIn the VHDL code, both synchronous and asynchronous resets are implemented as separate processes.\nYou can toggle the reset signal in the testbench to observe the different behaviors.\nExample VHDL Code Snippet for a 2-bit Synchronous Counter:\nlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;\nentity synchronous_counter is    Port ( clk : in STD_LOGIC;           reset : in STD_LOGIC;           count : out STD_LOGIC_VECTOR(1 downto 0));end synchronous_counter;\narchitecture Behavioral of synchronous_counter is    signal count_reg : STD_LOGIC_VECTOR(1 downto 0) := \"00\";begin    process(clk)    begin        if rising_edge(clk) then            if reset = '1' then                count_reg \u003c= \"00\";  -- Reset counter            else                count_reg \u003c= count_reg + 1;  -- Increment counter            end if;        end if;    end process;\n    count \u003c= count_reg;end Behavioral;\n\n4. Testbench for Simulation\nYou can create a simple testbench to stimulate the counter with a clock and reset signal:\nlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;\nentity tb_synchronous_counter isend tb_synchronous_counter;\narchitecture behavior of tb_synchronous_counter is    signal clk : STD_LOGIC := '0';    signal reset : STD_LOGIC := '0';    signal count : STD_LOGIC_VECTOR(1 downto 0);        -- Instantiate the counter    component synchronous_counter        Port ( clk : in STD_LOGIC;               reset : in STD_LOGIC;               count : out STD_LOGIC_VECTOR(1 downto 0));    end component;\nbegin    uut: synchronous_counter port map (clk, reset, count);\n    -- Clock generation    clk_process : process    begin        clk \u003c= not clk after 10 ns;        wait for 10 ns;    end process;\n    -- Stimulus process    stimulus: process    begin        -- Apply reset and observe behavior        reset \u003c= '1';        wait for 20 ns;        reset \u003c= '0';        wait for 100 ns;                -- Apply reset again        reset \u003c= '1';        wait for 20 ns;        reset \u003c= '0';        wait for 100 ns;\n        -- End simulation        wait;    end process;\nend behavior;\n\n5. Visualizing the Output\nOnce the simulation is complete, you can visualize the output waveforms in the ModelSim waveform viewer. You can check the timing diagram for the clock, reset, and counter output to verify the design.\nLicense\nThis project is licensed under the GNU General Public License v3.0. You can freely modify and redistribute the code, as long as any modifications are also shared under the same license.\nSummary of the GNU GPL v3.0 License:\n•\tYou can use, modify, and distribute the software as long as you make the source code available to others.\n•\tAny derivative works must also be licensed under the GPL v3.0.\n•\tYou cannot impose any additional restrictions on the rights granted by the license.\nFor more details, see the full GPLv3 License.\nContributing\nWe welcome contributions to improve the functionality, features, and performance of the counter designs.\nTo contribute:\n1.\tFork the repository.\n2.\tCreate a new branch for your feature or fix.\n3.\tMake your changes.\n4.\tEnsure that the code passes all tests.\n5.\tSubmit a pull request with a detailed description of your changes.\nAcknowledgements\n•\tThis project was inspired by educational tools and simulation environments used to teach digital electronics and hardware design concepts.\n•\tThanks to the ModelSim-Altera team for providing a robust simulation platform.\nContact\nFor questions, issues, or support, please open an issue on the GitHub repository.\nEnd of ReadMe.\nGNU General Public License v3.0\nhttps://www.vhdl-online.de/vhdl_workshop/start more VHDL projects\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fengineermichael%2Fmodelsim-altera-project-electronics-","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fengineermichael%2Fmodelsim-altera-project-electronics-","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fengineermichael%2Fmodelsim-altera-project-electronics-/lists"}