{"id":27180423,"url":"https://github.com/equation-man/risc-vmm","last_synced_at":"2025-04-09T14:36:06.119Z","repository":{"id":270975625,"uuid":"910534936","full_name":"equation-man/risc-vmm","owner":"equation-man","description":"RISC-Virtual Microprocessor Machine","archived":false,"fork":false,"pushed_at":"2025-01-04T13:21:25.000Z","size":7,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-31T08:41:21.354Z","etag":null,"topics":["emulation","microprocessor","risc-v-architecture","system-programming","virtual-machine"],"latest_commit_sha":null,"homepage":"","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/equation-man.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-12-31T14:55:33.000Z","updated_at":"2025-03-31T05:00:45.000Z","dependencies_parsed_at":null,"dependency_job_id":"e69b08c0-8bb1-4464-bf51-de3ca49df36f","html_url":"https://github.com/equation-man/risc-vmm","commit_stats":null,"previous_names":["alchemistprimus/risc-vmm","equation-man/risc-vmm"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/equation-man%2Frisc-vmm","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/equation-man%2Frisc-vmm/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/equation-man%2Frisc-vmm/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/equation-man%2Frisc-vmm/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/equation-man","download_url":"https://codeload.github.com/equation-man/risc-vmm/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248055290,"owners_count":21040151,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["emulation","microprocessor","risc-v-architecture","system-programming","virtual-machine"],"created_at":"2025-04-09T14:36:05.688Z","updated_at":"2025-04-09T14:36:06.113Z","avatar_url":"https://github.com/equation-man.png","language":"Rust","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC Virtual Microprocessor Machine (RISC-VMM)\n\nThis is a RISC-V based CPU emulator software.It assumes a relaxed version of RV32E CPU's instruction set architecture for resource \nconstrained embedded hardware, emulating how machine code is executed to provide an abstraction of how software controls the CPU \nhardware of a computer.\n\n## Short glossary:   \n\n#### Instructions   \nThese are primitive CPU commands. They loosely follow RISC-V instruction set architecture (RV32E).\nThey include moving data, working with memory and primitive arithmetic operations, e.g add, sub, mul, div, lw, sw   \n\n#### Machine code   \nCode that our CPU directly processes. Each instruction is encoded in 32 bits (4 bytes).   \n\n#### Opcode   \nThis is a number that maps to an operation. It is important to help determine how the instruction will be executed\n\n#### Registers   \nFixed set of temporary storage placeholders for operands in the CPU. Here, we have 16 general purpose registers \nwhich are x0, x1, ..., x15 and other special registers like the program counter(pc) which stores an instruction pointer \nwhich points to the location in RAM where it's going to fetch the next instruction.   \n\nUses load/store memory architecture. Instructions can only operate directly on the data in the registers. \nDedicated instructions, lw and sw are used to load or store data from or to the processor's internal registers.  \nThe processor can only execute instructions on the data stored in the registers as operands, in a fetch-decode-execute cycle.\n\n## Dependencies.   \n- Rust  \n- rustc  \n- Cargo  \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fequation-man%2Frisc-vmm","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fequation-man%2Frisc-vmm","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fequation-man%2Frisc-vmm/lists"}