{"id":13643764,"url":"https://github.com/f32c/f32c","last_synced_at":"2025-04-21T02:31:35.885Z","repository":{"id":30921017,"uuid":"34478922","full_name":"f32c/f32c","owner":"f32c","description":"A 32-bit MIPS / RISC-V core \u0026 SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz","archived":false,"fork":false,"pushed_at":"2025-04-20T15:21:28.000Z","size":12184,"stargazers_count":413,"open_issues_count":22,"forks_count":105,"subscribers_count":49,"default_branch":"master","last_synced_at":"2025-04-20T16:29:11.346Z","etag":null,"topics":["altera","arduino","fpga","lattice","mips","riscv","xilinx"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-2-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/f32c.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":"CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2015-04-23T20:09:23.000Z","updated_at":"2025-04-20T15:21:31.000Z","dependencies_parsed_at":"2023-01-14T18:00:15.844Z","dependency_job_id":"26580390-f44f-42bc-8094-70274dfb594d","html_url":"https://github.com/f32c/f32c","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/f32c%2Ff32c","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/f32c%2Ff32c/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/f32c%2Ff32c/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/f32c%2Ff32c/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/f32c","download_url":"https://codeload.github.com/f32c/f32c/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":249986070,"owners_count":21356318,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","arduino","fpga","lattice","mips","riscv","xilinx"],"created_at":"2024-08-02T01:01:52.303Z","updated_at":"2025-04-21T02:31:30.869Z","avatar_url":"https://github.com/f32c.png","language":"C","funding_links":[],"categories":["C"],"sub_categories":[],"readme":"# f32c\n\n[f32c](/rtl/cpu/README.md) is a retargetable, scalar, pipelined, 32-bit processor core which\ncan execute subsets of either RISC-V or MIPS instruction sets.\nIt is implemented in parametrized VHDL which permits synthesis with\ndifferent area / speed tradeoffs, and includes a branch predictor,\nexception handling control block, and optional direct-mapped caches.\nThe RTL code also includes [SoC](/rtl/soc/README.md) modules such as a \nmulti-port SDRAM and SRAM controllers, video framebuffers with composite (PAL),\nHDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows,\nfloating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a \ntimer, as well as glue logic tailored for numerous popular FPGA development boards \nfrom various manufacturers.\n\nIn synthetic integer benchmarks the core yields 3.3 CoreMark/MHz\nand 1.46 DMIPS/MHz with code and data stored in on-chip block RAMs.\nWhen configured with 16 KB of instruction and 8 KB of data cache,\nand with code and data stored in external SDRAM, the core yields\n3.13 CoreMark/MHz and 1.39 DMIPS/MHz.\n\nA performance-tuned f32c SoC which includes a timer\nand an UART occupies only 1048 6-input LUTs, while still being able to\nexecute gcc-generated code when synthesized in the most compact\nconfiguration which consumes just 697 (649 logic plus 48 memory) LUTs.\n\nFloating point vector processor can be optionally synthesized.\nTested on Xilinx Spartan-6 (xc6slx25) and 7-series (xc7a35i, xc7a102t, xc7z010),\nAltera Cyclone-4 (EP4CE22) and MAX-10 (10M50DAF), Lattice ECP3 (LFE3-150EA) \nand ECP5 (LFE5UM-85F). On Artix-7 it uses 3148 LUTs, 64K BRAM,\n38 DSP multipliers (36 for divider unit) and can provide up to 3 MFLOPs/MHz.\n\nThe Fmax depends on core configuration and FPGA silicon, and tops at\naround 115 MHz for 90 nm FPGAs (such as Xilinx S3E / S3A or Lattice XP2)\nup to 185 MHz for latest generations of 6-input LUT FPGAs such as\nArtix-7.\n\nConfigurable options include:\n\n```\nC_arch               RISC-V or MIPS ISA\nC_big_endian         bus endianess\nC_mult_enable        synthesize multipler unit\nC_branch_likely      support branch delay slot annulling\nC_sign_extend        support sign extension instructions\nC_movn_movz          support conditional move instructions\nC_ll_sc              support atomic read-modify-write constructs\nC_branch_prediction  synthesize branch predictor\nC_bp_global_depth    global branch history trace size\nC_result_forwarding  synthesize result bypasses\nC_load_aligner \t     synthesize load aligner\nC_full_shifter \t     pipelined instead of iterative shifer\nC_icache_size        instruction cache size (0 to 64 KB)\nC_dcache_size        data cache size (0 to 64 KB)\nC_debug              synthesize single-stepping debug module\n```\n\nPre-compiled gcc-based toolchains for Windows, OS-X and Linux can be\nfound at the [FPGArduino page](http://www.nxlab.fer.hr/fpgarduino),\ntogether with pre-built demo bitstreams for various Xilinx, Altera\nand Lattice FPGAs, and with further instructions on how to compile\nRISC-V / MIPS executables using the Arduino IDE.\n\nAll VHDL modules are [BSD licensed](LICENSE).  The majority of software\nlibraries are borrowed from FreeBSD, while some originate from other\nprojects and may be subject to an MIT-style license.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ff32c%2Ff32c","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ff32c%2Ff32c","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ff32c%2Ff32c/lists"}