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Notebook","funding_links":[],"categories":["Jupyter Notebook","FPGA Design"],"sub_categories":[],"readme":"\u003cp align=\"center\"\u003e\n  \u003ca title=\"Website\" href=\"https://f4pga.org\"\u003e\u003cimg src=\"https://img.shields.io/website?longCache=true\u0026style=flat-square\u0026label=f4pga.org\u0026up_color=10cfc9\u0026url=https%3A%2F%2Ff4pga.org%2Findex.html\u0026labelColor=fff\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n  \u003ca title=\"Documentation\" href=\"https://f4pga.readthedocs.io\"\u003e\u003cimg src=\"https://img.shields.io/website?longCache=true\u0026style=flat-square\u0026label=Documentation\u0026up_color=1226aa\u0026up_message=%E2%9E%9A\u0026url=https%3A%2F%2Ff4pga.readthedocs.io%2Fen%2Flatest%2Findex.html\u0026labelColor=fff\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n  \u003ca title=\"Community\" href=\"https://f4pga.readthedocs.io/en/latest/community.html#communication\"\u003e\u003cimg src=\"https://img.shields.io/badge/Chat-IRC%20%7C%20Slack-white?longCache=true\u0026style=flat-square\u0026logo=Slack\u0026logoColor=fff\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n\u003c/p\u003e\n\n# F4PGA Architecture Definitions\n\n\u003cp align=\"center\"\u003e\n  \u003ca title=\"License Status\" href=\"https://github.com/SymbiFlow/f4pga-arch-defs/blob/main/COPYING\"\u003e\u003cimg alt=\"License Status\" src=\"https://img.shields.io/github/license/SymbiFlow/f4pga-arch-defs?longCache=true\u0026style=flat-square\u0026label=License\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n  \u003ca title=\"Documentation Status\" href=\"https://f4pga.readthedocs.io/projects/arch-defs/\"\u003e\u003cimg alt=\"Documentation Status\" src=\"https://img.shields.io/readthedocs/symbiflow-arch-defs/latest?longCache=true\u0026style=flat-square\u0026logo=ReadTheDocs\u0026logoColor=fff\u0026label=Architecture%20Definitions%20Documentation\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n  \u003ca title=\"'Automerge' workflow status\" href=\"https://github.com/SymbiFlow/f4pga-arch-defs/actions/workflows/Automerge.yml\"\u003e\u003cimg alt=\"'Automerge' workflow status\" src=\"https://img.shields.io/github/actions/workflow/status/SymbiFlow/f4pga-arch-defs/Automerge.yml?branch=main\u0026longCache=true\u0026style=flat-square\u0026label=Tests\u0026logo=Github%20Actions\u0026logoColor=fff\"\u003e\u003c/a\u003e\u003c!--\n  --\u003e\n\u003c/p\u003e\n\n**This repository is focused on the development of architecture support in F4PGA. Start with the [![Examples (for Users)](https://img.shields.io/website?longCache=true\u0026style=flat-square\u0026label=F4PGA%20Examples%20for%20Users\u0026up_color=white\u0026up_message=%E2%9E%9A\u0026url=https%3A%2F%2Ff4pga-examples.readthedocs.io%2Fen%2Flatest%2Findex.html\u0026labelColor=231f20)](https://f4pga-examples.readthedocs.io) if you are looking to use the\ntools.**\n\nThis repo contains documentation of various FPGA architectures, it is currently concentrating on:\n\n* Lattice\n  * [iCE40](lattice/ice40)\n  * [ECP5](lattice/ecp5)\n* AMD/Xilinx\n  * [Series 7](xilinx/xc7) (Artix, Kintex and Zynq)\n* [QuickLogic](quicklogic)\n\nIt includes:\n\n* Black box part definitions\n* Verilog To Routing architecture definitions\n* Documentation for humans\n* Verilog simulations\n\nThe aim is to gather useful documentation (both human and machine readable) about the primitives and routing\ninfrastructure for these architectures.\nWe hope this enables growth in the open source FPGA tools space.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ff4pga%2Ff4pga-arch-defs","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ff4pga%2Ff4pga-arch-defs","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ff4pga%2Ff4pga-arch-defs/lists"}