{"id":28157108,"url":"https://github.com/focus04/big-alu","last_synced_at":"2026-01-29T07:02:28.070Z","repository":{"id":291761859,"uuid":"978680236","full_name":"Focus04/big-alu","owner":"Focus04","description":"Processor-like ALU Module","archived":false,"fork":false,"pushed_at":"2025-05-08T19:29:37.000Z","size":6,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-06-09T12:06:04.741Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Focus04.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2025-05-06T11:00:11.000Z","updated_at":"2025-05-08T19:29:40.000Z","dependencies_parsed_at":"2025-05-06T12:48:57.578Z","dependency_job_id":"c1ee78e6-a800-4071-a96a-cd1f8f10bd32","html_url":"https://github.com/Focus04/big-alu","commit_stats":null,"previous_names":["focus04/big-alu"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Focus04/big-alu","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Focus04%2Fbig-alu","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Focus04%2Fbig-alu/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Focus04%2Fbig-alu/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Focus04%2Fbig-alu/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Focus04","download_url":"https://codeload.github.com/Focus04/big-alu/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Focus04%2Fbig-alu/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28868877,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-29T06:56:44.678Z","status":"ssl_error","status_checked_at":"2026-01-29T06:56:35.794Z","response_time":59,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-05-15T08:16:16.992Z","updated_at":"2026-01-29T07:02:23.063Z","avatar_url":"https://github.com/Focus04.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Processor-like ALU\n\n## Overview\nThis project implements a configurable arithmetic logic unit (ALU) with multiple operations selectable via a 16-bit instruction input. It processes two 8-bit data inputs and produces four 8-bit outputs, along with status flags.\n\n## Module Hierarchy\n```\ntop.sv  \n├── shift_right.sv  \n├── shift_left.sv  \n├── add.sv  \n├── sub.sv  \n├── and_gate.sv  \n├── or_gate.sv  \n├── xor_gate.sv  \n├── special.sv  \n├── comp_eq.sv  \n├── mux4.sv  \n└── demux4.sv\n```\n\n## Inputs and Outputs\n\n### Inputs:\n- `instruction[15:0]`: 16-bit control word  \n- `data0[7:0]`: First 8-bit data input  \n- `data1[7:0]`: Second 8-bit data input  \n\n### Outputs:\n- `out0[7:0]` to `out3[7:0]`: Four 8-bit output channels  \n- `of`: Overflow flag (from addition operation)  \n- `zf`: Zero flag (output is zero)  \n\n## Instruction Decoding\n\n### Output Selection (`instruction[15:14]`):\n- `00`: Route to `out0`  \n- `01`: Route to `out1`  \n- `10`: Route to `out2`  \n- `11`: Route to `out3`  \n\n### Operation Category Selection (`instruction[13:12]`):\n- `00`: Arithmetic operations (mux0 output)  \n- `01`: Logical operations (mux1 output)  \n- `10`: Constant zero  \n- `11`: Special operation result  \n\n### Operation Selection within Category (`instruction[11:10]`):\n\n#### For Arithmetic operations (mux0):\n- `00`: Right shift  \n- `01`: Left shift  \n- `10`: Addition  \n- `11`: Subtraction  \n\n#### For Logical operations (mux1):\n- `00`: AND  \n- `01`: OR  \n- `10`: XOR  \n- `11`: Constant 1  \n\n## Supported Operations\n\n### Shift Operations:\n- Right shift: `data0 \u003e\u003e data1`  \n- Left shift: `data0 \u003c\u003c data1`  \n\n### Arithmetic Operations:\n- Addition: `data0 + data1` (with overflow flag)  \n- Subtraction: `data0 - data1`  \n\n### Logical Operations:\n- Bitwise AND: `data0 \u0026 data1`  \n- Bitwise OR: `data0 | data1`  \n- Bitwise XOR: `data0 ^ data1`  \n\n### Special Operation:\n- Checks if all four corner bits (LSB and MSB of both inputs) are equal  \n- Returns `1` if true, `0` otherwise  \n\n### Other:\n- Constant `0` output  \n- Constant `1` output (via logical operations only)  \n\n## Status Flags\n- `of`: Overflow Flag – Set when addition operation overflows  \n- `zf`: Zero Flag – Set when the selected output equals zero  \n\n## Example Usage\n\nThe following test bench module can be found within the source code and can be simulated with software such as Vivado.\n```verilog\n`timescale 1ns / 1ps\n\nmodule tb();\nlogic [15:0]instruction;\nlogic [7:0]data0, data1, out0, out1, out2, out3;\nlogic of, zf;\n\ntop dut(instruction, data0, data1, out0, out1, out2, out3, of, zf);\ninitial begin\n    instruction = 0;\n    data0 = 0;\n    data1 = 0;\n    #10\n      instruction = 16'b1111111111111111;\n    #10\n      data0 = 255;\n      data1 = 255;\n    #10\n      instruction = 16'b0000100000000000;\n      data0 = 1;\n      data1 = 1;\n    #5\n      data0 = 75;\n    #5\n      data1 = 25;\n    #10\n      $stop;\nend\nendmodule\n```\n\n## Timing\n- All operations are combinational and complete in zero time  \n- Timescale: `1ns/1ps` precision  \n\n## Dependencies\n- SystemVerilog-compliant simulator (Vivado, ModelSim, VCS)  \n- All source files must be compiled together  \n\n## Limitation\nThis is purely a combinational circuit and has no clock input.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffocus04%2Fbig-alu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffocus04%2Fbig-alu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffocus04%2Fbig-alu/lists"}