{"id":50688052,"url":"https://github.com/fpgadeveloper/2x-qsfp28-fmc","last_synced_at":"2026-06-09T00:33:02.303Z","repository":{"id":362348549,"uuid":"1258241251","full_name":"fpgadeveloper/2x-qsfp28-fmc","owner":"fpgadeveloper","description":"Reference designs for the Opsero 2x QSFP28 FMC","archived":false,"fork":false,"pushed_at":"2026-06-03T19:31:55.000Z","size":1328,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-06-03T21:12:42.101Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/fpgadeveloper.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2026-06-03T11:56:08.000Z","updated_at":"2026-06-03T19:31:59.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/fpgadeveloper/2x-qsfp28-fmc","commit_stats":null,"previous_names":["fpgadeveloper/2x-qsfp28-fmc"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/fpgadeveloper/2x-qsfp28-fmc","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2F2x-qsfp28-fmc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2F2x-qsfp28-fmc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2F2x-qsfp28-fmc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2F2x-qsfp28-fmc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/fpgadeveloper","download_url":"https://codeload.github.com/fpgadeveloper/2x-qsfp28-fmc/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2F2x-qsfp28-fmc/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":34086664,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-06-08T02:00:07.615Z","response_time":111,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2026-06-09T00:33:02.206Z","updated_at":"2026-06-09T00:33:02.298Z","avatar_url":"https://github.com/fpgadeveloper.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 100G Ethernet Reference Design for the Opsero 2x QSFP28 FMC\n\n## Description\n\nThis project demonstrates the use of the Opsero [2x QSFP28 FMC] (OP120) with 100G QSFP28 modules\non AMD Versal adaptive SoC development boards. Each QSFP28 port is driven by the Versal\n[Integrated 100G Multirate Ethernet MAC (MRMAC)] configured for a single 100GbE (CAUI-4) channel,\nwith packet data moved to/from DDR by an AXI MCDMA and driven under PetaLinux by the AXI Ethernet\ndriver.\n\n![2x QSFP28 FMC with VCK190](docs/source/images/vck190-with-2x-qsfp28-fmc_03.jpg \"2x QSFP28 FMC with VCK190\")\n\nImportant links:\n\n* The user guide for these reference designs is hosted here: [100G Ethernet for 2x QSFP28 FMC docs](https://qsfp28.ethernetfmc.com \"100G Ethernet for 2x QSFP28 FMC docs\")\n* To report a bug: [Report an issue](https://github.com/fpgadeveloper/2x-qsfp28-fmc/issues \"Report an issue\").\n* For technical support: [Contact Opsero](https://opsero.com/contact-us \"Contact Opsero\").\n* To purchase the mezzanine card: [2x QSFP28 FMC order page](https://opsero.com/product/2x-qsfp28-fmc \"2x QSFP28 FMC order page\").\n\n## Requirements\n\nThis project is designed for version 2025.2 of the Xilinx tools (Vivado/Vitis/PetaLinux).\nIf you are using an older version of the Xilinx tools, then refer to the\n[release tags](https://github.com/fpgadeveloper/2x-qsfp28-fmc/tags \"releases\")\nto find the version of this repository that matches your version of the tools.\n\nIn order to test this design on hardware, you will need the following:\n\n* Vivado 2025.2\n* PetaLinux Tools 2025.2\n* [2x QSFP28 FMC]\n* One of the target platforms listed below\n* [AMD Versal Integrated MRMAC License](https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/mrmac.html)\n\n## Target designs\n\nThis repo contains one or more designs that target various supported development boards and their\nFMC connectors. The table below lists the target design name, the QSFP28 ports supported by the design and\nthe FMC connector on which to connect the 2x QSFP28 FMC.\n\n\u003c!-- updater start --\u003e\n### 100G designs\n\n| Target board          | Target design      | Link speeds \u003cbr\u003e supported | QSFP28 ports | FMC Slot    | Vivado\u003cbr\u003e Edition |\n|-----------------------|--------------------|------------|-------------|-------------|-------|\n| [VCK190]              | `vck190_fmcp1`     | 100G       | 2x          | FMCP1       | Enterprise |\n\n[VCK190]: https://www.xilinx.com/vck190\n\u003c!-- updater end --\u003e\n\nNotes:\n1. The Vivado Edition column indicates which designs are supported by the Vivado *Standard* Edition, the\n   FREE edition which can be used without a license. Vivado *Enterprise* Edition requires\n   a license however a 30-day evaluation license is available from the AMD Xilinx Licensing site.\n2. The Versal Integrated MRMAC requires a (free) license to generate a bitstream.\n\n## Software\n\nThese reference designs can be driven within a PetaLinux environment.\nThe repository includes all necessary scripts and code to build the PetaLinux environments. The table\nbelow outlines the corresponding applications available in each environment:\n\n| Environment      | Available Applications  |\n|------------------|-------------------------|\n| PetaLinux        | Built-in Linux commands\u003cbr\u003eAdditional tools: ethtool, iperf3 |\n\n## Build instructions\n\nClone the repo:\n```\ngit clone https://github.com/fpgadeveloper/2x-qsfp28-fmc.git\n```\n\nSource Vivado and PetaLinux tools:\n\n```\nsource \u003cpath-to-petalinux\u003e/2025.2/settings.sh\nsource \u003cpath-to-xilinx-tools\u003e/2025.2/Vivado/settings64.sh\n```\n\nBuild all (Vivado project and PetaLinux):\n\n```\ncd 2x-qsfp28-fmc/PetaLinux\nmake petalinux TARGET=vck190_fmcp1\n```\n\n## Troubleshooting\n\n### PetaLinux build fails with `bitbake petalinux-image-minimal failed` and sstate fetch errors\n\nIf a `make petalinux TARGET=\u003cboard\u003e` run ends with errors like\n\n```\nERROR: \u003cpackage\u003e-\u003cver\u003e-r0 do_..._setscene: Fetcher failure: Unable to find file file://.../sstate:...\n[ERROR] Command bitbake petalinux-image-minimal failed\n```\n\nthe actual build is not broken. These `_setscene` errors come from\nbitbake trying to pull prebuilt artifacts from the public Xilinx\nsstate-cache mirror, which occasionally returns 404 for individual\npackages. Bitbake falls back to building those packages locally and\nsucceeds, but still exits non-zero because of the failed fetches —\nso the Makefile stops before the `petalinux-package` step that\nproduces `BOOT.BIN`.\n\n**Fix: just re-run the same command.** The second attempt finds the\nmissing packages in the local sstate cache (populated by the first\nrun) and completes cleanly, producing `BOOT.BIN`. The reference\ndesign itself is fine; this is a transient issue with the public\nmirror.\n\n## Contribute\n\nWe strongly encourage community contribution to these projects. Please make a pull request if you\nwould like to share your work:\n* if you've spotted and fixed any issues\n* if you've added designs for other target platforms\n\nThank you to everyone who supports us!\n\n## About us\n\nThis project was developed by [Opsero Inc.](https://opsero.com \"Opsero Inc.\"),\na tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies.\nFollow our blog, [FPGA Developer](https://www.fpgadeveloper.com \"FPGA Developer\"), for news, tutorials and\nupdates on the awesome projects we work on.\n\n[2x QSFP28 FMC]: https://docs.opsero.com/op120/datasheet/overview/\n[Integrated 100G Multirate Ethernet MAC (MRMAC)]: https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/mrmac.html\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2F2x-qsfp28-fmc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffpgadeveloper%2F2x-qsfp28-fmc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2F2x-qsfp28-fmc/lists"}