{"id":48842953,"url":"https://github.com/fpgadeveloper/ethernet-fmc-max-axi-eth","last_synced_at":"2026-04-15T03:04:05.806Z","repository":{"id":257577513,"uuid":"856891648","full_name":"fpgadeveloper/ethernet-fmc-max-axi-eth","owner":"fpgadeveloper","description":"AXI 1G Ethernet ref designs for the Opsero Ethernet FMC Max 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AXI 1G Ethernet Ref Designs for Ethernet FMC Max\n\n## Description\n\nThis project demonstrates the use of the Opsero [Ethernet FMC Max] (OP080) and it supports\nseveral development boards for UltraScale FPGA, Zynq UltraScale+ and Versal ACAP. \nThe design contains 4 AXI 1G Ethernet Subsystem blocks configured with DMAs.\n\n![Application example](docs/source/images/ethernet-fmc-max-with-vek280.jpg \"Ethernet FMC Max with VEK280\")\n\nImportant links:\n\n* The user guide for these reference designs is hosted here: [AXI Ethernet for Ethernet FMC Max docs](https://axieth-sgmii.ethernetfmc.com \"AXI Ethernet for Ethernet FMC Max docs\")\n* To report a bug: [Report an issue](https://github.com/fpgadeveloper/ethernet-fmc-max-axi-eth/issues \"Report an issue\").\n* For technical support: [Contact Opsero](https://opsero.com/contact-us \"Contact Opsero\").\n* To purchase the mezzanine card: [Ethernet FMC Max order page](https://opsero.com/product/ethernet-fmc-max \"Ethernet FMC Max order page\").\n\n## Requirements\n\nThis project is designed for version 2024.1 of the Xilinx tools (Vivado/Vitis/PetaLinux). \nIf you are using an older version of the Xilinx tools, then refer to the \n[release tags](https://github.com/fpgadeveloper/ethernet-fmc-max-axi-eth/tags \"releases\")\nto find the version of this repository that matches your version of the tools.\n\nIn order to test this design on hardware, you will need the following:\n\n* Vivado 2024.1\n* Vitis 2024.1\n* PetaLinux Tools 2024.1\n* [Ethernet FMC Max]\n* One of the target platforms listed below\n* [Xilinx Soft TEMAC license](https://ethernetfmc.com/getting-a-license-for-the-xilinx-tri-mode-ethernet-mac/ \"Xilinx Soft TEMAC license\")\n\n## Target designs\n\nThis repo contains several designs that target various supported development boards and their\nFMC connectors. The table below lists the target design name, the number of ports supported by the design and \nthe FMC connector on which to connect the mezzanine card. Some of the target designs\nrequire a license to generate a bitstream with the AMD Xilinx tools.\n\n\u003c!-- updater start --\u003e\n### Zynq UltraScale+ designs\n\n| Target board          | Target design      | Ports       | FMC Slot    | Standalone\u003cbr\u003e Echo Server | PetaLinux | Vivado\u003cbr\u003e Edition |\n|-----------------------|--------------------|-------------|-------------|-------|-------|-------|\n| [UltraZed-EV Carrier] | `uzev`             | 4x          | HPC         | :white_check_mark: | :white_check_mark: | Standard :free: |\n| [ZCU102]              | `zcu102_hpc0`      | 4x          | HPC0        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [ZCU102]              | `zcu102_hpc1`      | 4x          | HPC1        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [ZCU104]              | `zcu104`           | 1x          | LPC         | :white_check_mark: | :white_check_mark: | Standard :free: |\n| [ZCU106]              | `zcu106_hpc0`      | 4x          | HPC0        | :white_check_mark: | :white_check_mark: | Standard :free: |\n| [ZCU111]              | `zcu111`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [ZCU208]              | `zcu208`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [ZCU216]              | `zcu216`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n\n### Versal designs\n\n| Target board          | Target design      | Ports       | FMC Slot    | Standalone\u003cbr\u003e Echo Server | PetaLinux | Vivado\u003cbr\u003e Edition |\n|-----------------------|--------------------|-------------|-------------|-------|-------|-------|\n| [VCK190]              | `vck190_fmcp1`     | 4x          | FMCP1       | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VCK190]              | `vck190_fmcp2`     | 4x          | FMCP2       | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VEK280]              | `vek280`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VHK158]              | `vhk158`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VMK180]              | `vmk180_fmcp1`     | 4x          | FMCP1       | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VMK180]              | `vmk180_fmcp2`     | 4x          | FMCP2       | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VPK120]              | `vpk120`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [VPK180]              | `vpk180`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n\n[UltraZed-EV Carrier]: https://www.xilinx.com/products/boards-and-kits/1-1s78dxb.html\n[ZCU102]: https://www.xilinx.com/zcu102\n[ZCU104]: https://www.xilinx.com/zcu104\n[ZCU106]: https://www.xilinx.com/zcu106\n[ZCU111]: https://www.xilinx.com/zcu111\n[ZCU208]: https://www.xilinx.com/zcu208\n[ZCU216]: https://www.xilinx.com/zcu216\n[VCK190]: https://www.xilinx.com/vck190\n[VEK280]: https://www.xilinx.com/vek280\n[VHK158]: https://www.xilinx.com/vhk158\n[VMK180]: https://www.xilinx.com/vmk180\n[VPK120]: https://www.xilinx.com/vpk120\n[VPK180]: https://www.xilinx.com/vpk180\n\u003c!-- updater end --\u003e\n\nNotes:\n\n1. The Vivado Edition column indicates which designs are supported by the Vivado *Standard* Edition, the\n   FREE edition which can be used without a license. Vivado *Enterprise* Edition requires\n   a license however a 30-day evaluation license is available from the AMD Xilinx Licensing site.\n\n## Software\n\nThese reference designs can be driven by either a standalone application or within a PetaLinux environment. \nThe repository includes all necessary scripts and code to build both environments. The table \nbelow outlines the corresponding applications available in each environment:\n\n| Environment      | Available Applications  |\n|------------------|-------------------------|\n| Standalone       | lwIP Echo Server |\n| PetaLinux        | Built-in Linux commands\u003cbr\u003eAdditional tools: ethtool, phytool, iperf3 |\n\n## Build instructions\n\nClone the repo:\n```\ngit clone https://github.com/fpgadeveloper/ethernet-fmc-max-axi-eth.git\n```\n\nSource Vivado and PetaLinux tools:\n\n```\nsource \u003cpath-to-petalinux\u003e/2024.1/settings.sh\nsource \u003cpath-to-vivado\u003e/2024.1/settings64.sh\n```\n\nTo build the standalone lwIP echo server application (Vivado project and Vitis workspace):\n\n```\ncd ethernet-fmc-max-axi-eth/Vitis\nmake workspace TARGET=zcu106_hpc0\n```\n\nTo build the PetaLinux image (Vivado project and PetaLinux):\n\n```\ncd ethernet-fmc-max-axi-eth/PetaLinux\nmake petalinux TARGET=zcu106_hpc0\n```\n\nReplace the target label in these commands with the one corresponding to the target design of your\nchoice from the tables above.\n\n## Contribute\n\nWe strongly encourage community contribution to these projects. Please make a pull request if you\nwould like to share your work:\n* if you've spotted and fixed any issues\n* if you've added designs for other target platforms\n\nThank you to everyone who supports us!\n\n## About us\n\nThis project was developed by [Opsero Inc.](https://opsero.com \"Opsero Inc.\"),\na tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. \nFollow our blog, [FPGA Developer](https://www.fpgadeveloper.com \"FPGA Developer\"), for news, tutorials and\nupdates on the awesome projects we work on.\n\n[Ethernet FMC Max]: https://ethernetfmc.com/docs/ethernet-fmc-max/overview/\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-axi-eth","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-axi-eth","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-axi-eth/lists"}