{"id":50948737,"url":"https://github.com/fpgadeveloper/ethernet-fmc-max-ps-gem","last_synced_at":"2026-06-17T23:03:47.323Z","repository":{"id":365221501,"uuid":"1265369464","full_name":"fpgadeveloper/ethernet-fmc-max-ps-gem","owner":"fpgadeveloper","description":"PS GEM based reference designs for the Opsero Ethernet FMC Max (OP080)","archived":false,"fork":false,"pushed_at":"2026-06-16T11:24:55.000Z","size":1508,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-06-16T12:26:44.723Z","etag":null,"topics":["ethernet","fpga","versal","zynqmp"],"latest_commit_sha":null,"homepage":"https://docs.opsero.com/op080/datasheet/overview/","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/fpgadeveloper.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2026-06-10T17:58:52.000Z","updated_at":"2026-06-16T10:57:25.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/fpgadeveloper/ethernet-fmc-max-ps-gem","commit_stats":null,"previous_names":["fpgadeveloper/ethernet-fmc-max-ps-gem"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/fpgadeveloper/ethernet-fmc-max-ps-gem","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-ps-gem","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-ps-gem/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-ps-gem/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-ps-gem/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/fpgadeveloper","download_url":"https://codeload.github.com/fpgadeveloper/ethernet-fmc-max-ps-gem/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-ps-gem/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":34468767,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-06-17T02:00:05.408Z","response_time":127,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["ethernet","fpga","versal","zynqmp"],"created_at":"2026-06-17T23:03:46.132Z","updated_at":"2026-06-17T23:03:47.316Z","avatar_url":"https://github.com/fpgadeveloper.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"# PS GEM Reference Designs for the Opsero Ethernet FMC Max (OP080)\n\n## Description\n\nThis project demonstrates the use of the Opsero [Ethernet FMC Max] (OP080) with the hard\ngigabit Ethernet MACs (GEMs) of the Zynq UltraScale+ and Versal processing systems.\nEach port of the mezzanine card is driven by a PS GEM routed through EMIO GMII into the\nprogrammable logic, where an Ethernet PCS/PMA or SGMII core (PG047) converts the GMII to\nSGMII over a gigabit transceiver lane connected to the port's TI DP83867 PHY. No soft MAC\nor DMA IP is used — the ports are handled by the standard PS GEM software drivers.\n\n![Ethernet FMC Max with ZCU106](docs/source/images/zcu106-with-op080_03.jpg)\n\nImportant links:\n\n* The user guide for these reference designs is hosted here: [Ethernet FMC Max PS GEM docs](https://psgem-sgmii.ethernetfmc.com \"Ethernet FMC Max PS GEM docs\")\n* To report a bug: [Report an issue](https://github.com/fpgadeveloper/ethernet-fmc-max-ps-gem/issues \"Report an issue\").\n* For technical support: [Contact Opsero](https://opsero.com/contact-us \"Contact Opsero\").\n* To purchase the mezzanine card: [Ethernet FMC Max order page](https://opsero.com/product/ethernet-fmc-max \"Ethernet FMC Max order page\").\n\n## Requirements\n\nThis project is designed for version 2025.2 of the Xilinx tools (Vivado/Vitis/PetaLinux). \nIf you are using an older version of the Xilinx tools, then refer to the \n[release tags](https://github.com/fpgadeveloper/ethernet-fmc-max-ps-gem/tags \"releases\")\nto find the version of this repository that matches your version of the tools.\n\nIn order to test this design on hardware, you will need the following:\n\n* Vivado 2025.2\n* Vitis 2025.2\n* PetaLinux Tools 2025.2\n* [Ethernet FMC Max]\n* One of the target platforms listed below\n\n## Target designs\n\nThis repo contains several designs that target various supported development boards and their\nFMC connectors. The table below lists the target design name, the number of ports supported by the design and \nthe FMC connector on which to connect the mezzanine card. Some of the target designs\nrequire a license to generate a bitstream with the AMD Xilinx tools.\n\n\u003c!-- updater start --\u003e\n### Zynq UltraScale+ designs\n\n| Target board          | Target design      | Ports       | FMC Slot    | Standalone\u003cbr\u003e Echo Server | PetaLinux | Vivado\u003cbr\u003e Edition |\n|-----------------------|--------------------|-------------|-------------|-------|-------|-------|\n| [UltraZed-EV Carrier] | `uzev`             | 4x          | HPC         | :white_check_mark: | :white_check_mark: | Standard :free: |\n| [ZCU102]              | `zcu102_hpc0`      | 4x          | HPC0        | :white_check_mark: | :white_check_mark: | Enterprise |\n| [ZCU106]              | `zcu106_hpc0`      | 4x          | HPC0        | :white_check_mark: | :white_check_mark: | Standard :free: |\n| [ZCU111]              | `zcu111`           | 4x          | FMCP        | :white_check_mark: | :white_check_mark: | Enterprise |\n\n### Versal designs\n\n| Target board          | Target design      | Ports       | FMC Slot    | Standalone\u003cbr\u003e Echo Server | PetaLinux | Vivado\u003cbr\u003e Edition |\n|-----------------------|--------------------|-------------|-------------|-------|-------|-------|\n| [VCK190]              | `vck190_fmcp1`     | 2x          | FMCP1       | :white_check_mark: | :white_check_mark: | Enterprise |\n\n[UltraZed-EV Carrier]: https://www.xilinx.com/products/boards-and-kits/1-1s78dxb.html\n[ZCU102]: https://www.xilinx.com/zcu102\n[ZCU106]: https://www.xilinx.com/zcu106\n[ZCU111]: https://www.xilinx.com/zcu111\n[VCK190]: https://www.xilinx.com/vck190\n\u003c!-- updater end --\u003e\n\n### UltraZed-EV board files\n\nThe board definition files for the UltraZed-EV Carrier are not currently included in the AMD Xilinx Board Store.\nTo enable Vivado to recognize this board, the required board files have been included in this\nrepository as a Git submodule (`submodules/avnet-bdf`), which is a fork of\n[Avnet's BDF repository](https://github.com/Avnet/bdf). When cloning this repo, use the `--recursive`\nflag to ensure the board files are downloaded:\n\n```\ngit clone --recursive \u003crepo-url\u003e\n```\n\nNotes:\n\n1. The Vivado Edition column indicates which designs are supported by the Vivado *Standard* Edition, the\n   FREE edition which can be used without a license. Vivado *Enterprise* Edition requires\n   a license however a 30-day evaluation license is available from the AMD Xilinx Licensing site.\n2. The VCK190 design supports ports 0 and 1 of the Ethernet FMC Max only, because the Versal PS\n   has two GEM controllers. The PHYs of ports 2 and 3 are held in reset in that design.\n3. Because the GEMs are routed to the FMC through EMIO in these designs, the development\n   board's onboard Ethernet ports are not available.\n\n## Software\n\nThese reference designs can be driven by either a standalone application or within a PetaLinux environment. \nThe repository includes all necessary scripts and code to build both environments. The table \nbelow outlines the corresponding applications available in each environment:\n\n| Environment      | Available Applications  |\n|------------------|-------------------------|\n| Standalone       | lwIP Echo Server |\n| PetaLinux        | Built-in Linux commands\u003cbr\u003eAdditional tools: ethtool, phytool, iperf3 |\n\n## Build instructions\n\nClone the repo:\n```\ngit clone --recursive https://github.com/fpgadeveloper/ethernet-fmc-max-ps-gem.git\n```\n\nSource Vivado and PetaLinux tools:\n\n```\nsource \u003cpath-to-petalinux\u003e/2025.2/settings.sh\nsource \u003cpath-to-xilinx-tools\u003e/2025.2/Vivado/settings64.sh\n```\n\nTo build the standalone lwIP echo server application (Vivado project and Vitis workspace):\n\n```\ncd ethernet-fmc-max-ps-gem/Vitis\nmake workspace TARGET=zcu106_hpc0\n```\n\nTo build the PetaLinux image (Vivado project and PetaLinux):\n\n```\ncd ethernet-fmc-max-ps-gem/PetaLinux\nmake petalinux TARGET=zcu106_hpc0\n```\n\nReplace the target label in these commands with the one corresponding to the target design of your\nchoice from the tables above.\n\n## Troubleshooting\n\n### PetaLinux build fails with `bitbake petalinux-image-minimal failed` and sstate fetch errors\n\nIf a `make petalinux TARGET=\u003cboard\u003e` run ends with errors like\n\n```\nERROR: \u003cpackage\u003e-\u003cver\u003e-r0 do_..._setscene: Fetcher failure: Unable to find file file://.../sstate:...\n[ERROR] Command bitbake petalinux-image-minimal failed\n```\n\nthe actual build is not broken. These `_setscene` errors come from\nbitbake trying to pull prebuilt artifacts from the public Xilinx\nsstate-cache mirror, which occasionally returns 404 for individual\npackages. Bitbake falls back to building those packages locally and\nsucceeds, but still exits non-zero because of the failed fetches —\nso the Makefile stops before the `petalinux-package` step that\nproduces `BOOT.BIN`.\n\n**Fix: just re-run the same command.** The second attempt finds the\nmissing packages in the local sstate cache (populated by the first\nrun) and completes cleanly, producing `BOOT.BIN`. The reference\ndesign itself is fine; this is a transient issue with the public\nmirror.\n\n\n## Contribute\n\nWe strongly encourage community contribution to these projects. Please make a pull request if you\nwould like to share your work:\n* if you've spotted and fixed any issues\n* if you've added designs for other target platforms\n\nThank you to everyone who supports us!\n\n## About us\n\nThis project was developed by [Opsero Inc.](https://opsero.com \"Opsero Inc.\"),\na tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. \nFollow our blog, [FPGA Developer](https://www.fpgadeveloper.com \"FPGA Developer\"), for news, tutorials and\nupdates on the awesome projects we work on.\n\n[Ethernet FMC Max]: https://docs.opsero.com/op080/datasheet/overview/\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-ps-gem","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-ps-gem","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-ps-gem/lists"}