{"id":13649179,"url":"https://github.com/fpgadeveloper/ethernet-fmc-max-throughput","last_synced_at":"2026-03-13T02:33:51.806Z","repository":{"id":23098146,"uuid":"26452237","full_name":"fpgadeveloper/ethernet-fmc-max-throughput","owner":"fpgadeveloper","description":"Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput","archived":false,"fork":false,"pushed_at":"2024-11-20T20:57:04.000Z","size":14607,"stargazers_count":11,"open_issues_count":0,"forks_count":8,"subscribers_count":3,"default_branch":"master","last_synced_at":"2024-11-20T21:43:54.088Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"http://ethernetfmc.com","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/fpgadeveloper.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2014-11-10T19:38:21.000Z","updated_at":"2024-11-20T20:56:50.000Z","dependencies_parsed_at":"2022-08-21T11:40:09.645Z","dependency_job_id":"3742ebd3-0680-4393-9e4b-9a1512573821","html_url":"https://github.com/fpgadeveloper/ethernet-fmc-max-throughput","commit_stats":null,"previous_names":[],"tags_count":13,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-throughput","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-throughput/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-throughput/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fpgadeveloper%2Fethernet-fmc-max-throughput/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/fpgadeveloper","download_url":"https://codeload.github.com/fpgadeveloper/ethernet-fmc-max-throughput/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258817,"owners_count":21400975,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:49.382Z","updated_at":"2025-12-18T01:31:58.744Z","avatar_url":"https://github.com/fpgadeveloper.png","language":"Tcl","funding_links":[],"categories":["Tcl"],"sub_categories":[],"readme":"# Max Throughput Example Design for Ethernet FMC\n\nExample design for the Opsero [Ethernet FMC] and [Robust Ethernet FMC] using an FPGA based hardware\npacket generator/checker to demonstrate maximum throughput.\n\n## Requirements\n\nThis project is designed for version 2024.1 of the Xilinx tools (Vivado/SDK/PetaLinux). If you are using an older version of the \nXilinx tools, then refer to the [release tags](https://github.com/fpgadeveloper/ethernet-fmc-max-throughput/tags \"releases\")\nto find the version of this repository that matches your version of the tools.\n\nIn order to test the Ethernet FMC using this design, you need to use an\nEthernet cable to loopback ports 0 and 2, and ports 1 and 3.\nYou will also need the following:\n\n* Vivado 2024.1\n* Vitis 2024.1\n* Vivado HLS 2024.1\n* [Ethernet FMC] or [Robust Ethernet FMC]\n* Supported FMC carrier board (see list of supported carriers below)\n* Two Ethernet cables\n* [Xilinx Soft TEMAC license](https://ethernetfmc.com/getting-a-license-for-the-xilinx-tri-mode-ethernet-mac/ \"Xilinx Soft TEMAC license\")\n\n## Supported carrier boards\n\n* Zynq-7000 [ZedBoard](http://zedboard.org \"ZedBoard\")\n  * LPC connector\n\n## Description\n\nThis project is used for testing the [Ethernet FMC] or [Robust Ethernet FMC] at\nmaximum throughput. The design contains 4 AXI Ethernet blocks and 4\nhardware traffic generators. The transmitted frames contain fixed destination and source MAC addresses,\nthe Ethertype, a payload of random data and the FCS checksum.\n\n![Ethernet FMC Max Throughput Test design](docs/source/images/max-tp-block-diagram.png \"Ethernet FMC Max Throughput Test design\")\n\n## Build instructions for Windows users\n\n### Build Vivado project in Windows\n\n1. Download the repo as a zip file and extract the files to a directory\n   on your hard drive --OR-- clone the repo to your hard drive\n2. Open Windows Explorer, browse to the repo files on your hard drive.\n3. In the `Vivado` directory, double click on the `build-vivado.bat` batch file.\n   You will be prompted to select a target design to build. You will find the project in\n   the folder `Vivado/\u003ctarget\u003e`.\n4. Run Vivado and open the project that was just created.\n5. Click Generate bitstream.\n6. When the bitstream is successfully generated, select **File-\u003eExport-\u003eExport Hardware**.\n   In the window that opens, tick **Include bitstream** and use the default name and location\n   for the XSA file.\n\n### Build Vitis workspace in Windows\n\nBefore running these steps, you must first build and export the Vivado project as described above.\n\n1. Return to Windows Explorer and browse to the Vitis directory in the repo.\n2. Double click the `build-vitis.bat` batch file. You will be prompted to select a target design.\n   A Vitis workspace with hardware platform and software application will be created for the\n   selected target design. You will find the Vitis workspace in the folder `Vitis/\u003ctarget\u003e_workspace`.\n\n## Build instructions for Linux users\n\n### Build Vivado project in Linux\n\n1. Open a command terminal and launch the setup script for Vivado:\n   ```\n   source \u003cpath-to-vivado-install\u003e/2024.1/settings64.sh\n   ```\n2. Clone the Git repository and `cd` into the `Vivado` folder of the repo:\n   ```\n   git clone https://github.com/fpgadeveloper/ethernet-fmc-max-throughput.git\n   cd ethernet-fmc-max-throughput/Vivado\n   ```\n3. Run make to create the Vivado project for the target board. You must replace `\u003ctarget\u003e` with a valid\n   target (alternatively, skip to step 5):\n   ```\n   make project TARGET=\u003ctarget\u003e\n   ```\n   Valid targets are: \n   `zedboard`.\n   That will create the Vivado project and block design without generating a bitstream or exporting to XSA.\n4. Open the generated project in the Vivado GUI and click **Generate Bitstream**. Once the build is\n   complete, select **File-\u003eExport-\u003eExport Hardware** and be sure to tick **Include bitstream** and use\n   the default name and location for the XSA file.\n5. Alternatively, you can create the Vivado project, generate the bitstream and export to XSA (steps 3 and 4),\n   all from a single command:\n   ```\n   make xsa TARGET=\u003ctarget\u003e\n   ```\n   \n### Build Vitis workspace in Linux\n\nThe following steps are required if you wish to build and run the [standalone application](stand_alone). You \nare not required to have built the Vivado design before following these steps, as the Makefile triggers the \nVivado build for the corresponding design if it has not already been done.\n\n1. Launch the setup script for Vivado (only if you skipped the Vivado build steps above):\n   ```\n   source \u003cpath-to-vivado-install\u003e/2024.1/settings64.sh\n   ```\n2. Launch the setup scripts for Vitis:\n   ```\n   source \u003cpath-to-vitis-install\u003e/2024.1/settings64.sh\n   ```\n3. To build the Vitis workspace, `cd` to the Vitis directory in the repo,\n   then run make to create the Vitis workspace and compile the standalone application:\n   ```\n   cd ethernet-fmc-max-throughput/Vitis\n   make workspace TARGET=\u003ctarget\u003e\n   ```\n   You will find the Vitis workspace in the folder `Vitis/\u003ctarget\u003e_workspace`.\n\n## Background\n\nIn order to test an Ethernet device at maximum throughput (back-to-back\npackets at 1Gbps), one could setup the MACs to loopback to each other\nand then send packets to each port from an external source such as a PC\nwhich could compare the returned packets to the sent ones. However, it\nis generally difficult to use a PC Ethernet port at full throughput,\nbecause a PC typically has too many overheads which create a delay\nbetween consecutive packets. For this reason, this design uses four\nhardware packet generator/checkers that are implemented in the FPGA.\nThese generator/checkers drive the AXI Ethernet cores (the MACs) with a\ncontinuous stream of packets. By using the FPGA to generate the Ethernet\npackets, we are able to exploit almost 100% of the potential bandwidth.\n\n## MAC Setup\n\nThe software application sets up the MACs in promiscuous mode which\nallows them to pass through all packets, regardless of their destination\nMAC address. It also sets them up to receive the FCS (checksum) from the\nuser design, rather than calculating and inserting it itself.\n\n## Detecting Bit Errors\n\n### Counting Dropped Frames\n\nDue to the FCS (checksum) which is present in every Ethernet packet, most bit\nerrors that are injected into the system will result in dropped packets at\nthe receiving MAC (ie. the receiving MAC will reject packets where the FCS does\nnot match the frame data). Therefore, our primary method for detection of bit\nerrors involves polling the MACs for rejected frames. The number of rejected\nframes is tracked by the software application.\n\nTo ensure that the MACs are truly rejecting frames with bit errors, we inject\none bit error into one packet per second, on all 4 ports. Our design supplies\nthe FCS to the transmit interface of the MACs, rather than having the MACs \ncalculate and append the FCS. This allows us to inject a bit error that should\nrender the FCS incorrect for the frame.\n\n## Ethernet Traffic Generator IP\n\nThe traffic generator IP was designed in Vivado HLS (High-level Synthesis) and is coded\nin C++. Vivado HLS allows hardware algorithms to be programmed in the C/C++ language which\noffers tremendous advantages over VHDL and Verilog, especially when developing packet processing \nsystems. This example design serves as a good platform for developing Ethernet packet\nprocessing algorithms with the Ethernet FMC.\n\n## Simulation\n\nThe Ethernet Traffic Generator IP can be simulated in Vivado by using the RTL testbench that\nis included with the project. The Vivado project contains two block designs, `maxtp` and `maxtp_sim`,\nused for implementation and simulation respectively. The `maxtp_sim` block design contains one\ninstantiation of the Ethernet Traffic Generator IP (the DUT) and one AXI VPI IP core that we use to initialize the\nsoftware registers of the DUT. To run the simulation, simply open the Vivado project and select \nRun Simulation-\u003eRun Behavioral Simulation.\n\n## Other applications\n\nThis design is actually used as a production test for the [Ethernet FMC] and [Robust Ethernet FMC]\nbecause it places maximum stress on the PHYs, which forces the maximum\ncurrent consumption, heat dissipation and possibility for cross-talk\nbetween lanes. It can however be a very useful design for people who\nneed to communicate over Ethernet with another FPGA or an Ethernet\ndevice that can support the high throughput.\n\n## Troubleshooting\n\nCheck the following if the project fails to build or generate a bitstream:\n\n### 1. Are you using the correct version of Vivado for this version of the repository?\nCheck the version specified in the Requirements section of this readme file. Note that this project is regularly maintained to the latest\nversion of Vivado and you may have to refer to an earlier commit of this repo if you are using an older version of Vivado.\n\n### 2. Did you follow the Build instructions in this readme file?\nAll the projects in the repo are built, synthesised and implemented to a bitstream before being committed, so if you follow the\ninstructions, there should not be any build issues.\n\n### 3. Did you copy/clone the repo into a short directory structure?\nVivado doesn't cope well with long directory structures, so copy/clone the repo into a short directory structure such as\n`C:\\projects\\`. When working in long directory structures, you can get errors relating to missing files, particularly files \nthat are normally generated by Vivado (FIFOs, etc).\n\n## Contribute\n\nWe encourage contribution to these projects. If you spot issues or you want to add designs for other platforms, please\nmake a pull request.\n\n## About us\n\nThis project was developed by [Opsero Inc.](http://opsero.com \"Opsero Inc.\"),\na tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. \nFollow our blog, [FPGA Developer](http://www.fpgadeveloper.com \"FPGA Developer\"), for news, tutorials and\nupdates on the awesome projects we work on.\n\n[Ethernet FMC]: https://ethernetfmc.com/docs/ethernet-fmc/overview/\n[Robust Ethernet FMC]: https://ethernetfmc.com/docs/robust-ethernet-fmc/overview/\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-throughput","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-throughput","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffpgadeveloper%2Fethernet-fmc-max-throughput/lists"}