{"id":22194149,"url":"https://github.com/francoriba/mipspipeline","last_synced_at":"2026-01-05T09:06:48.583Z","repository":{"id":259629859,"uuid":"834633749","full_name":"francoriba/MIPSPipeline","owner":"francoriba","description":"Repository for development of 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MIPS Pipeline implemented in Basys3 FPGA\nAll the details of this implementation can be found in the .pdf file\n\n## Debug Unit State Machine \n\n``` mermaid\nstateDiagram-v2\n    [*] --\u003e STATE_IDLE\n    STATE_IDLE --\u003e STATE_ACTIVATE_READER_BUFFER: uart_read\n    STATE_ACTIVATE_READER_BUFFER --\u003e STATE_READ\n    STATE_READ --\u003e STATE_CMD_INSTRUCTION: i_uart_read_finish\n    STATE_CMD_INSTRUCTION --\u003e STATE_FLUSH: \"L\" or \"C\" or \"S\"\n    STATE_CMD_INSTRUCTION --\u003e STATE_IDLE: default\n    STATE_FLUSH --\u003e STATE_LOAD_INSTRUCTION: \"L\"\n    STATE_FLUSH --\u003e STATE_RUN_CONTINUOUS: \"C\"\n    STATE_FLUSH --\u003e STATE_PRINT_REGS_START: \"S\"\n    STATE_LOAD_INSTRUCTION --\u003e STATE_ACTIVATE_READER_BUFFER: !i_instr_mem_full\n    STATE_LOAD_INSTRUCTION --\u003e STATE_ACTIVATE_WRITER_BUFFER: i_instr_mem_full\n    STATE_LOAD_INSTRUCTION --\u003e STATE_ACTIVATE_WRITER_BUFFER: HALT instruction\n    STATE_ACTIVATE_WRITER_BUFFER --\u003e STATE_WRITE\n    STATE_WRITE --\u003e STATE_IDLE: i_uart_write_finish\n    STATE_ACTIVATE_READER_BUFFER --\u003e STATE_CONTINUE_LOADING: from LOAD_INSTRUCTION\n    STATE_CONTINUE_LOADING --\u003e STATE_LOAD_INSTRUCTION\n    STATE_RUN_CONTINUOUS --\u003e STATE_PRINT_REGS_START: i_finish_program\n    STATE_RUN_CONTINUOUS --\u003e STATE_EMPTY_PROGRAM: i_instr_mem_empty\n    STATE_EMPTY_PROGRAM --\u003e STATE_ACTIVATE_WRITER_BUFFER\n    STATE_PRINT_REGS_START --\u003e STATE_PRINT_REGS\n    STATE_PRINT_REGS --\u003e STATE_PRINT_MEM_START: i_print_regs_finish\n    STATE_PRINT_MEM_START --\u003e STATE_PRINT_MEM\n    STATE_PRINT_MEM --\u003e STATE_FINISH_RUN: i_print_mem_finish\n    STATE_FINISH_RUN --\u003e STATE_ACTIVATE_WRITER_BUFFER: i_finish_program\n    STATE_FINISH_RUN --\u003e STATE_WAIT_NEXT_STEP: step_mode\n    STATE_WAIT_NEXT_STEP --\u003e STATE_ACTIVATE_READER_BUFFER\n    STATE_ACTIVATE_READER_BUFFER --\u003e STATE_RUN_STEP_INSTRUCTION: from WAIT_NEXT_STEP\n    STATE_RUN_STEP_INSTRUCTION --\u003e STATE_PRINT_REGS_START: \"N\" and !i_instr_mem_empty\n    STATE_RUN_STEP_INSTRUCTION --\u003e STATE_EMPTY_PROGRAM: \"N\" and i_instr_mem_empty\n    STATE_RUN_STEP_INSTRUCTION --\u003e STATE_WAIT_NEXT_STEP: not \"N\"\n```\n\n### State Machine Overview\n\n#### `STATE_IDLE`\n- **Description**: Initial state of the system. Reached after reset or when a command execution is completed.\n- **Use case**: Waiting for a new command.\n\n#### `STATE_ACTIVATE_READER_BUFFER`\n- **Transitions**:\n  - From `STATE_IDLE` when ready to read a command.\n  - From `STATE_LOAD_INSTRUCTION` when loading more instructions.\n  - From `STATE_WAIT_NEXT_STEP` in step mode.\n- **Use case**: Preparing to read data from UART.\n\n#### `STATE_READ`\n- **Transitions**: Always reached from `STATE_ACTIVATE_READER_BUFFER`.\n- **Use case**: Reading data from UART.\n\n#### `STATE_CMD_INSTRUCTION`\n- **Transitions**: Reached from `STATE_READ` when UART reading is complete.\n- **Use case**: Interpreting the received command (Load, Continuous, or Step mode).\n\n#### `STATE_FLUSH`\n- **Transitions**: Reached from `STATE_CMD_INSTRUCTION` for \"L\", \"C\", or \"S\" commands.\n- **Use case**: Resetting stages before executing a new command.\n\n#### `STATE_LOAD_INSTRUCTION`\n- **Transitions**:\n  - From `STATE_FLUSH` after \"L\" command.\n  - From `STATE_CONTINUE_LOADING` in a loop while loading instructions.\n- **Use case**: Loading a new program into instruction memory.\n\n#### `STATE_CONTINUE_LOADING`\n- **Transitions**: Reached from `STATE_READ` when loading instructions.\n- **Use case**: Continuing to load the next instruction.\n\n#### `STATE_RUN_CONTINUOUS`\n- **Transitions**: Reached from `STATE_FLUSH` after \"C\" command.\n- **Use case**: Running the program continuously.\n\n#### `STATE_PRINT_REGS_START`\n- **Transitions**:\n  - From `STATE_FLUSH` after \"S\" command (step mode).\n  - From `STATE_RUN_CONTINUOUS` when program finishes.\n  - From `STATE_RUN_STEP_INSTRUCTION` after each step.\n- **Use case**: Initiating the process of printing registers.\n\n#### `STATE_PRINT_REGS`\n- **Transitions**: Always reached from `STATE_PRINT_REGS_START`.\n- **Use case**: Printing register contents.\n\n#### `STATE_PRINT_MEM_START`\n- **Transitions**: Reached from `STATE_PRINT_REGS` when register printing is finished.\n- **Use case**: Initiating the process of printing memory.\n\n#### `STATE_PRINT_MEM`\n- **Transitions**: Always reached from `STATE_PRINT_MEM_START`.\n- **Use case**: Printing memory contents.\n\n#### `STATE_FINISH_RUN`\n- **Transitions**: Reached from `STATE_PRINT_MEM` when memory printing is finished.\n- **Use case**: Finalizing the execution of a step or the entire program.\n\n#### `STATE_ACTIVATE_WRITER_BUFFER`\n- **Transitions**:\n  - From `STATE_LOAD_INSTRUCTION` when instruction memory is full or HALT instruction is encountered.\n  - From `STATE_EMPTY_PROGRAM` to report an error.\n  - From `STATE_FINISH_RUN` to report step completion or program end.\n- **Use case**: Preparing to write data to UART.\n\n#### `STATE_WRITE`\n- **Transitions**: Always reached from `STATE_ACTIVATE_WRITER_BUFFER`.\n- **Use case**: Writing data to UART.\n\n#### `STATE_EMPTY_PROGRAM`\n- **Transitions**: Reached from `STATE_RUN_CONTINUOUS` or `STATE_RUN_STEP_INSTRUCTION` when instruction memory is empty.\n- **Use case**: Handling the case when there's no program loaded.\n\n#### `STATE_RUN_STEP_INSTRUCTION`\n- **Transitions**: Reached from `STATE_READ` after receiving \"N\" command in step mode.\n- **Use case**: Executing a single instruction in step mode.\n\n#### `STATE_WAIT_NEXT_STEP`\n- **Transitions**:\n  - From `STATE_RUN_STEP_INSTRUCTION` when not receiving \"N\" command.\n  - From `STATE_FINISH_RUN` in step mode.\n- **Use case**: Waiting for the next step command in step mode.\n\n###  Step-by-step mode\n\n* The system clock is always running, but the MIPS processor only executes instructions when mips_enabled is high.\n* In step-by-step mode, the mips_enabled signal is carefully controlled to allow only one instruction execution at a time. This is primarily handled in the STATE_RUN_STEP_INSTRUCTION state of the debug interface state machine.\n\n* When a step command (\"N\" for Next) is received, the system does the following:\n    * It sets mips_enabled_next to 1'b1, allowing the MIPS processor to execute one instruction.\n    * It then immediately transitions to STATE_PRINT_REGS_START, which will disable the MIPS processor after the instruction execution.\n*In the STATE_PRINT_REGS_START state, the system disables the MIPS processor\n* The system then goes through the process of printing registers and memory, before returning to STATE_FINISH_RUN and then STATE_WAIT_NEXT_STEP, where it waits for the next step command.\n\n\u003cimg src=\"/img/fsm.drawio.png\" alt=\"Descripción de la imagen\" width=\"120%\"\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffrancoriba%2Fmipspipeline","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffrancoriba%2Fmipspipeline","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffrancoriba%2Fmipspipeline/lists"}