{"id":13773811,"url":"https://github.com/freand76/digsim","last_synced_at":"2026-01-03T18:17:04.140Z","repository":{"id":65724311,"uuid":"576727294","full_name":"freand76/digsim","owner":"freand76","description":"An interactive digital logic simulator with verilog support (Yosys)","archived":false,"fork":false,"pushed_at":"2025-05-08T16:54:09.000Z","size":1522,"stargazers_count":19,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"main","last_synced_at":"2025-05-08T17:41:47.748Z","etag":null,"topics":["logic","python","rtl","simulation","simulator","vcd","verilog","yosys"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/freand76.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2022-12-10T19:30:42.000Z","updated_at":"2025-05-08T16:54:12.000Z","dependencies_parsed_at":"2025-05-08T17:39:08.715Z","dependency_job_id":null,"html_url":"https://github.com/freand76/digsim","commit_stats":null,"previous_names":[],"tags_count":9,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/freand76%2Fdigsim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/freand76%2Fdigsim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/freand76%2Fdigsim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/freand76%2Fdigsim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/freand76","download_url":"https://codeload.github.com/freand76/digsim/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253528361,"owners_count":21922623,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["logic","python","rtl","simulation","simulator","vcd","verilog","yosys"],"created_at":"2024-08-03T17:01:20.456Z","updated_at":"2026-01-03T18:17:04.135Z","avatar_url":"https://github.com/freand76.png","language":"Python","funding_links":[],"categories":["Digital Design"],"sub_categories":[],"readme":"# DigSim - Interactive Digital Logic Simulator\n\n![Python Version from PEP 621 TOML](https://img.shields.io/python/required-version-toml?tomlFilePath=https%3A%2F%2Fraw.githubusercontent.com%2Ffreand76%2Fdigsim%2Fmain%2Fpyproject.toml)\n![PyPI - Version](https://img.shields.io/pypi/v/digsim-logic-simulator)\n![PyPI - Downloads](https://img.shields.io/pypi/dm/digsim-logic-simulator)\n\n\u003cp align=\"center\"\u003e\n  \u003cimg alt=\"The DigSim Application\" src=\"https://raw.githubusercontent.com/freand76/digsim/af1bf95eb16d1af19f26159a4c1e1b88565703d7/docs/images/screenshot_digsim_app.png\" width=85%\u003e\n\u003c/p\u003e\n\n## Introduction\n\nDigSim is a python based framework for digital circuit simulation.\nThe main purpose of the software is to, in an educational way, play around with digital logic (simple gates and verilog designs).\n\nWhen working with block design in Verilog/VHDL the simulation tools are normally fed with test stimuli (a very non-interactive way of working...)\nA block design can be synthesized and tested on an FPGA (where there are possibilities for interactivity if buttons and LED/Hex digits are available),\nbut that often has a great cost in time (and sometimes money) leading to long turnaround time.\n\nI started developing DigSim to make it easy to implement and visualize the functionality of simple verlog modules.\nDuring development I tried to synthesize larger verilog designs, such as the classic [6502 CPU](https://en.wikipedia.org/wiki/MOS_Technology_6502),\nand even if it is slower than many other simulators it is not entirely useless.\n\n### Features\n * Create and simulate a circuit using python code\n * Create and simulate a circuit **interactively** using the GUI\n * Create new components using synthesized verilog code\n * Save simulation results in VCD files, which can be opened in for example GTKWave.\n\n## Quickstart\n\n### Install from PyPi (Option 1)\n```\npip3 install digsim-logic-simulator\n```\n\n### Install from GitHub (Option 2)\n```\n\u003e git clone https://github.com/freand76/digsim.git\n\u003e cd digsim\n\u003e python3 -m pip install .\n```\n\n### Start Interactive GUI\n\n**Prerequisites:** Install by using *Option 1* or *Option 2* above.\n\n```\n\u003e python3 -m digsim.app\n```\n\nor\n\n```\n\u003e digsim-logic-simulator\n```\n\n### Start using uv\n\n**Prerequisites:** Download and install [uv](https://docs.astral.sh/uv/)\n\n```\n\u003e uvx digsim-logic-simulator\n```\n\n**Note: Ubuntu**\n\nIf your Ubuntu installation gives the folloing error message:\n\n*qt.qpa.plugin: Could not load the Qt platform plugin \"xcb\" in \"\" even though it was found.*\n*This application failed to start because no Qt platform plugin could be initialized. Reinstalling the application may fix this problem.*\n\n*Available platform plugins are: vnc, wayland, wayland-egl, eglfs, offscreen, xcb, minimal, linuxfb, vkkhrdisplay, minimalegl.*\n\nThen the following package must be installed:\n```\n\u003e apt install libxcb-cursor0\n```\n\n### Start with example circuit (example circuits are available in the github repository)\n```\n\u003e python3 -m digsim.app --load example_circuits/counter_yosys_netlist.circuit\n```\n\n### Run example (examples are available in the github repository)\n```\n\u003e python3 examples/example_sr.py\n```\n\n### Look at waveforms\n```\n\u003e python3 examples/example_sr.py\n\u003e gtkwave sr.vcd\n```\n\n### Examples of writing pytest/python test benches for synthesized verilog code\n```\n\u003e pytest examples/pytest_tb\n```\n\n## Yosys synthesis helper tool\n\n```\n\u003e python3 -m digsim.synth synth -i \u003cverilog file 1\u003e \u003coptional verilog file 2\u003e -o \u003coutput_file.json\u003e -t \u003cverilog top_module\u003e\n```\n\n## Documentation\n\n[Documentation](https://github.com/freand76/digsim/blob/main/docs/documentation.md) on GitHub\n\n## Star History\n\n[![Star History Chart](https://api.star-history.com/svg?repos=freand76/digsim\u0026type=Date)](https://star-history.com/#freand76/digsim\u0026Date)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffreand76%2Fdigsim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffreand76%2Fdigsim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffreand76%2Fdigsim/lists"}