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This transformation can be applied through the \nuse of annotations as demonstrated in the examples.GCD test. The graphs are mostly clickable, clicking a module\nwill take you to a diagram for just that module. There is a TopLevel diagram that just shows the module hierarchy.\nAlso, an individual arrow can be hovered over to make it turn red and become easier to follow.\n\n## Example\n\n### Top Level Example\n![Graph](https://raw.githubusercontent.com/freechipsproject/diagrammer/master/images/TopLevel.dot.svg?sanitize=true)\n\n### Module Example\n\n![Graph](https://raw.githubusercontent.com/freechipsproject/diagrammer/master/images/TopOfVisualizer.dot.svg?sanitize=true)\n\n## Using\n### Install\nInstalling this software should be pretty much the following.\n```bash\ngit clone https://github.com/freechipsproject/diagrammer\ncd diagrammer\n```\n\n### Dependencies\nYou will need [GraphViz](https://www.graphviz.org/) (specifically a default path to the program `dot`) and `sbt`.\n\nNote that this project currently depends on the master branches of all components\nof the Chisel ecosystem (chisel3 and firrtl), so you will need to `clone` and `sbt publishLocal` for each of these.\n\n### Creating Circuit Diagrams.\nTo create a set of graphs of a Firrtl Circuit all you need is this project and a Firrtl file (typically a file \ngenerated by Chisel with a `.fir` extension). Let's say you have a Firrtl file `~/projects/output/circuit.fir`.\nFrom the command line you while in this directory for this project, you run\n```bash\n./diagram.sh -i ~/projects/output/circuit.fir\n```\nThis will create a number of files in the same directory as the firrtl file that representing the firrtl graph.\nEach file will be a diagram for each module\ncontained in the firrtl file, plus a file TopLevel.dot.svg file. It will also attempt to open the TopLevel.dot.svg file\nin a browser using the command `open`. \nEach Module in the TopLevel diagram is clickable and should take you into the diagram for that specific module.\nBecause of the size of these files, the diagrams will include the internal logic of that module plus and IO only\npresentation of any sub-modules found.\n\n## Options\n* -i, --firrtl-source set the source firrtl to work on\n* -t, --targer-dir sets the output directory for the svg\n* -s, --start-module sets the module name where the graphs will start being generated. The default is at the top\n* -o, --open-program sets the open program, default is `open`, set to empty to tell it not to do open\n* -j, --just-top-level generates just the top level diagram\n\n## How Diagrammer Works\nThis program uses a number of firrtl transforms to create multiple graphviz dot file graph programs.\nThe dot files are translated into .svg files. See [GeneratorBootcamp Firrtl Chapters](https://github.com/freechipsproject/chisel-bootcamp)\nfor a good introduction to writing Firrtl transforms\n\n## TODO\n- This used to work by annotating a circuit, consider re-adding that\n- Setting to allow the graphs to go deeper into sub-module logic\n- Provide links to the chisel source\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffreechipsproject%2Fdiagrammer","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffreechipsproject%2Fdiagrammer","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffreechipsproject%2Fdiagrammer/lists"}